中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.018 seconds)

    Dual casting PCIE inbound writes to memory and peer devices
    2.
    发明授权
    Dual casting PCIE inbound writes to memory and peer devices 有权
    双向PCIE入卡写入内存和对等设备

    公开(公告)号：US09189441B2

    公开(公告)日：2015-11-17

    申请号：US13656134

    申请日：2012-10-19

    Applicant: INTEL CORPORATION

    Inventor： Jayakrishna Guddeti ,  Luke Chang

    IPC: G06F13/14 ,  G06F13/40

    CPC classification number: G06F13/404 ,  G06F13/14 ,  G06F2213/0026

    Abstract: Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.

    Abstract translation: 用于支持从PCIe设备到存储器和对等PCIe设备的入站系统存储器双向注入的方法和设备。 在PCIe根组合处接收来自第一PCIe设备的入站系统存储器写入请求，并检查存储器地址以确定其是否落入为双重铸造操作定义的地址窗口内。 如果是这样，则从入站系统存储器写请求产生IO写请求，并将其发送到与地址窗口相关联的第二PCIe设备。 在并行操作期间，将原始入站系统内存写请求转发给配置为接收此类写请求的系统代理。

    POSTED INTERRUPT ARCHITECTURE
    4.
    发明申请
    POSTED INTERRUPT ARCHITECTURE 有权
    中断中断架构

    公开(公告)号：US20160147679A1

    公开(公告)日：2016-05-26

    申请号：US14553430

    申请日：2014-11-25

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti ,  Luke Chang ,  Rajesh M. Sankaran ,  Junaid F. Thaliyil

    IPC: G06F13/24 ,  G06F12/08

    CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F9/4812 ,  G06F12/0871 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2212/1032 ,  G06F2212/657

    Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

    Abstract translation: 从输入/输出（I / O）设备识别中断，特定高速缓存行的地址与中断相关联。 高速缓存行对应于中断的目的地，并表示中断的一个或多个属性。 一个请求被发送到一个并发代理以获取特定高速缓存行的所有权，并且发送一个请求，以便基于该中断在高速缓存行上执行读 - 修改 - 写（RMW）操作。

    Techniques to perform forward error correction for an electrical backplane
    8.
    发明授权
    Techniques to perform forward error correction for an electrical backplane 有权
    对电气背板进行前向纠错的技术

    公开(公告)号：US09544089B2

    公开(公告)日：2017-01-10

    申请号：US14698102

    申请日：2015-04-28

    Applicant: Intel Corporation

    Inventor： Ilango S. Ganga ,  Luke Chang ,  Andrey Belogolovy ,  Ovchinnikov Andrei

    IPC: H03M13/00 ,  H04L1/00 ,  H03M13/33 ,  H04L7/04 ,  G06F11/10 ,  H04L7/033

    CPC classification number: H04L1/0043 ,  G06F11/10 ,  H03M13/33 ,  H03M13/63 ,  H03M13/6312 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0072 ,  H04L7/041 ,  Y02D30/32

    Abstract: A media independent interface and circuitry of a forward error correction (FEC) sublayer are provided, the circuitry of the FEC sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer. The FEC sublayer include an encoder having a reverse gearbox, a compressor coupled to said reverse gearbox, a selector coupled to said compressor, a parity generator coupled to said compressor, a multiplexer coupled to said compressor, selector and said parity generator, a scrambler coupled to said multiplexer, and a pseudo-noise generator coupled to said scrambler.

    Abstract translation: 提供了前向纠错（FEC）子层的媒体独立接口和电路，FEC子层的电路执行前向纠错，FEC子层耦合到物理编码子层和物理介质附着（PMA）子层。 FEC子层包括具有倒档齿轮箱的编码器，耦合到所述倒档齿轮箱的压缩机，耦合到所述压缩器的选择器，耦合到所述压缩器的奇偶校验发生器，耦合到所述压缩器，选择器和所述奇偶校验发生器的多路复用器， 到所述多路复用器，以及耦合到所述加扰器的伪噪声发生器。

    METHOD, APPARATUS AND SYSTEM FOR INTEGRATING DEVICES IN A ROOT COMPLEX
    9.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR INTEGRATING DEVICES IN A ROOT COMPLEX 有权
    方法，装置和系统，用于在根复合体中集成装置

    公开(公告)号：US20160179738A1

    公开(公告)日：2016-06-23

    申请号：US14573738

    申请日：2014-12-17

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti ,  Luke Chang ,  Junaid F. Thaliyil ,  Chandra P. Joshi

    IPC: G06F13/42 ,  G06F11/30 ,  G06F13/24 ,  G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/4221 ,  G06F11/3027 ,  G06F13/1642 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4027

    Abstract: In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex including a first root port to interface to a first device to be coupled to the apparatus via a first interconnect and a second root port to interface to the agent via a bridge logic; and the bridge logic to interface the second root port to the agent, convert a first transaction from the first root port having a first format to a second format and communicate the first transaction having the second format to the agent. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种装置包括：半导体管芯，包括但不限于：执行指令的至少一个核心; 执行至少一个功能的代理; 根组合件，其包括第一根端口以与第一设备接口以经由第一互连耦合到所述设备，以及第二根端口以经由桥逻辑与所述代理接口; 以及用于将第二根端口连接到代理的桥接逻辑，将具有第一格式的第一根端口的第一事务转换为第二格式，并将具有第二格式的第一事务传递给代理。 描述和要求保护其他实施例。

Patent Agency Ranking