An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units. The memory units may each have a size less than a total size of the memory. The memory units may include a plurality of cells. The controller may be configured to issue a plurality of program operations to write to one or more of the cells. The controller may be configured to implement a polling status command after each of the program operations to verify programming of each of the cells. A response to each of the polling status commands may be used to report a number of the cells that failed to be programmed.