公开(公告)号：US10164657B2

公开(公告)日：2018-12-25

申请号：US15195879

申请日：2016-06-28

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch ,  Ning Chen

IPC: H03M13/11 ,  G11B20/18 ,  H03M13/00 ,  G06F11/10

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages.

公开(公告)号：US10020066B2

公开(公告)日：2018-07-10

申请号：US15626978

申请日：2017-06-19

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G11C16/34 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C16/3427 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a first voltage, programming a second cell of the solid state memory device to a second voltage different than the first voltage, detecting a voltage shift in the first cell when the second cell is being programmed; characterizing the first voltage of the first cell offset by the voltage shift as an interim voltage of the first cell, and repeatedly reading the interim voltage of the first cell using a first set of incrementally adjusted voltage values until an output of the first cell changes.

公开(公告)号：US20180011761A1

公开(公告)日：2018-01-11

申请号：US15700727

申请日：2017-09-11

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/0616 ,  G06F11/1016

Abstract: An apparatus comprises a memory and a controller. The memory generally comprises a plurality of memory modules, each having a size less than a total size of the memory and configured to store data. The controller may be configured to process a plurality of read/write operations, classify data pages from multiple blocks of the memory as hot-read data or non hot-read data, and aggregate the hot-read data by selecting one or more of the hot-read data pages from multiple memory blocks and mapping the selected hot-read data pages to dedicated hot-read data blocks using a strong type of error correcting code during one or more of a garbage collection state, a data recycling state, or an idle state. The aggregation of the hot-read data pages and use of the strong type of error correcting code reduces read latency of the hot-read data pages, reduces a frequency of data recycling of the hot-read data pages, and reduces an impact of read disturbs on endurance of the memory.

公开(公告)号：US09582361B2

公开(公告)日：2017-02-28

申请号：US14282380

申请日：2014-05-20

Applicant: Seagate Technology LLC

Inventor： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  H03M13/39

CPC classification number: H03M13/3927 ,  G06F8/65 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/3905 ,  H03M13/6325 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6588 ,  H03M13/6591

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.

Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器包括多个存储器单元，每个存储器单元的尺寸小于存储器的总大小。 控制器可以被配置为对存储器单元执行纠错码解码。 控制器可以被配置为生成各自包含实际值的多个原始对数似然比。 控制器可以被配置为将每个原始对数似然比转换成包括固定点值的转换对数似然比。 转换包括（a）缩小每个原始对数似然比的大小，以及（b）将具有缩小幅度的原始对数似然比中的每一个舍入到固定点值。

公开(公告)号：US09378090B2

公开(公告)日：2016-06-28

申请号：US14305208

申请日：2014-06-16

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C7/02 ,  G11C16/34 ,  G11C29/02 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1072 ,  G11C7/02 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller may perform a second read operation using a second read reference voltage. The controller may identify a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller may perform a third read operation on aggressor cells of the victim cell. The controller may perform a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells.

Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器可以包括多个存储器模块，每个存储器模块的尺寸小于存储器的总大小。 控制器可以被配置为在使用第一读取参考电压执行第一读取操作之后，恢复存储在存储器中的数据，该数据被确定为超过最大错误数。 控制器可以使用第二读取参考电压来执行第二读取操作。 控制器可以识别在第一读取参考电压和第二读取参考电压之间的区域中具有阈值电压的受害单元。 控制器可以对受害者单元的侵略者单元执行第三次读取操作。 控制器可以基于来自侵略者单元的干扰的类型，使用具有位固定值的第一读取参考电压来执行第四读取操作。

公开(公告)号：US09329935B2

公开(公告)日：2016-05-03

申请号：US14280884

申请日：2014-05-19

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Yu Cai ,  Erich F. Haratsch ,  Yunxiang Wu

IPC: H03M13/00 ,  H03M13/03 ,  G06F11/10 ,  H03M13/39

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  H03M13/3927

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units.

Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读/写操作。 存储器包括多个存储器单元，每个存储器单元的尺寸小于存储器的总大小。 控制器可以被配置为使用多个初始对数似然比值对存储器单元执行第一纠错码解码。 如果第一纠错码解码失败，则控制器可以被配置为对不满足的检查数进行计数。 如果不满足的检查的数量低于阈值，则控制器可以被配置为生成多个测量的对数似然比值。 多个测量对数似然比值是（a）基于使用第一纠错码解码的解码比特的计算，和（b）用于对存储器单元执行第二纠错码解码。

公开(公告)号：US09323607B2

公开(公告)日：2016-04-26

申请号：US14273920

申请日：2014-05-09

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/10 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F11/1024 ,  G06F11/1064 ,  G06F11/1076 ,  G11C16/3436 ,  G11C16/349 ,  G11C29/04 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/72 ,  G11C2029/0409

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page.

Abstract translation: 一种包括存储器和控制器的装置。 存储器被配置为处理多个读/写操作。 存储器包括多个存储器模块，每个存储器模块的尺寸小于存储器的总大小。 控制器被配置为打捞存储在存储器的故障页面中的数据，其被确定为超过最大错误数量。 控制器复制存储在失败页面中的原始数据。 控制器识别无法擦除识别的第一类数据单元的位置。 控制器识别具有程序错误的第二类型的数据单元的位置。 控制器在第一类型的数据单元的位置和第二类型的数据单元的位置翻转原始数据中的数据值。 控制器被配置为对具有翻转数据值的原始数据执行纠错码解码。 控制器抢救存储在失败页面中的数据。

公开(公告)号：US09319073B2

公开(公告)日：2016-04-19

申请号：US14194180

申请日：2014-02-28

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Ivana Djurdjevic ,  Yu Cai ,  Erich F. Haratsch ,  Yue Li ,  Earl T. Cohen

IPC: H04L1/00 ,  H03M13/35 ,  G06F11/10 ,  H03M13/09 ,  H03M13/11 ,  H03M13/13 ,  H03M13/29

CPC classification number: H03M13/35 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/2906

Abstract: An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.

Abstract translation: 一种装置包括控制器和自适应纠错码解码器。 控制器可以被配置为从存储器设备读取数据并写入数据。 控制器还可以被配置为以两步过程写入数据，其包括（i）在将数据写入最低有效位（LSB）页面之后，使用第一强度纠错码（LSB）检查存储在LSB页中的数据 ECC）解码过程，并且（ii）在将数据写入与LSB页面相关联的最高有效位（MSB）页面之后，使用第二强度纠错码（ECC）解码处理来检查存储在LSB和MSB页面中的数据。

公开(公告)号：US09262268B2

公开(公告)日：2016-02-16

申请号：US14173108

申请日：2014-02-05

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Ning Chen ,  Yunxiang Wu ,  Erich F. Haratsch ,  Earl T. Cohen ,  Timothy L. Canepa

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072

Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

Abstract translation: 一种装置包括存储器和控制器。 存储器包括多个存储器件。 每个存储器设备具有多个页面类型。 基于错误率变化对多个页面类型进行分类。 控制器可以被配置为将用户数据和纠错数据写入存储器。 用户数据和纠错数据被组织为超级页面。 超级页面包括多个子页面。 多个子页面被跨越多个存储器件写入，使得使用多个页面类型中的多个页面类型存储多个子页面。

公开(公告)号：US20150340100A1

公开(公告)日：2015-11-26

申请号：US14284875

申请日：2014-05-22

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G06F11/1048 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/34 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/program operations. The memory may comprise a plurality of memory units. The memory units may each have a size less than a total size of the memory. The memory units may include a plurality of cells. The controller may be configured to issue a plurality of program operations to write to one or more of the cells. The controller may be configured to implement a polling status command after each of the program operations to verify programming of each of the cells. A response to each of the polling status commands may be used to report a number of the cells that failed to be programmed.

Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为处理多个读取/编程操作。 存储器可以包括多个存储器单元。 存储器单元可以各自具有小于存储器的总大小的尺寸。 存储器单元可以包括多个单元。 控制器可以被配置为发出多个程序操作以写入一个或多个单元。 控制器可以被配置为在每个程序操作之后实现轮询状态命令，以验证每个单元的编程。 可以使用对每个轮询状态命令的响应来报告无法编程的单元的数量。