Invention Grant
- Patent Title: Method of forming semiconductor structure with aligning mark in dicing region
-
Application No.: US15487396Application Date: 2017-04-13
-
Publication No.: US09960123B2Publication Date: 2018-05-01
- Inventor: Ying-Chiao Wang , Yu-Hsiang Hung , Chao-Hung Lin , Ssu-I Fu , Chih-Kai Hsu , Jyh-Shyang Jenq
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agency: Winston Hsu
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/28 ; H01L21/033 ; H01L21/311

Abstract:
The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.
Public/Granted literature
- US20170221834A1 METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH ALIGNING MARK Public/Granted day:2017-08-03
Information query
IPC分类: