公开(公告)号：US11387148B2

公开(公告)日：2022-07-12

申请号：US16872395

申请日：2020-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/324 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

公开(公告)号：US09722078B2

公开(公告)日：2017-08-01

申请号：US14855390

申请日：2015-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending downwardly from a top end and at least occupying 80% to 90% of the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

公开(公告)号：US09553026B1

公开(公告)日：2017-01-24

申请号：US14960447

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chien-Ting Lin ,  Li-Chiang Chen ,  Jyh-Shyang Jenq

IPC: H01L21/30 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.

Abstract translation: 公开了半导体器件的制造方法。 首先，设置基板，在基板上形成第一芯轴，第二心轴，第三心轴，第四心轴。 优选地，第一心轴和第二心轴包括其间的第一间隙，第二心轴和第三心轴在其间包括第二间隙，并且第三心轴和第四心轴在其间包括第三间隙，其中第一间隙等于 第三个差距，但与第二个差距不同。 接下来，在第一心轴，第二心轴，第三心轴和第四心轴附近形成间隔物，并且去除第一间隙和第三间隙中的间隔物。

公开(公告)号：US20160365344A1

公开(公告)日：2016-12-15

申请号：US14792591

申请日：2015-07-06

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US09502410B1

公开(公告)日：2016-11-22

申请号：US14792591

申请日：2015-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US20160233088A1

公开(公告)日：2016-08-11

申请号：US14637400

申请日：2015-03-04

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/225 ,  H01L27/092 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个鳍状结构的基底，其中鳍状结构包括顶部和底部; 以及围绕所述鳍状结构的底部部分形成掺杂层和第一衬垫。

公开(公告)号：US09349833B1

公开(公告)日：2016-05-24

申请号：US14614416

申请日：2015-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ying-Tsung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Shih-Hung Tsai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.

Abstract translation: 半导体器件包括多个栅极结构，源极/漏极区，第一电介质层和浮置间隔物。 栅极结构设置在衬底上，并且每个栅极结构包括栅电极，覆盖层和围绕栅电极和覆盖层的间隔物。 源极/漏极区域设置在栅电极的两侧。 第一介电层设置在基板上，其高度小于栅电极的高度。 浮动间隔件设置在间隔件的侧壁上，也位于第一介电层上。

公开(公告)号：US10103062B2

公开(公告)日：2018-10-16

申请号：US14814516

申请日：2015-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L21/308 ,  H01L29/06 ,  H01L21/28

Abstract: A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure.

公开(公告)号：US09954108B2

公开(公告)日：2018-04-24

申请号：US15458035

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.

公开(公告)号：US20180108656A1

公开(公告)日：2018-04-19

申请号：US15347797

申请日：2016-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

Abstract: An asymmetrical fin structure includes a substrate. The substrate includes a top surface. A fin element extends from the substrate and connects to the substrate. The fin element includes two sidewalls respectively disposed at two opposite sides of the fin element. The sidewalls contact the top surface of the substrate. An epitaxial layer contacts and only covers one of the sidewalls. The other sidewall on the fin element does not contact any epitaxial layer.