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公开(公告)号：EP3328558A4
公开(公告)日：2018-08-01
申请号：EP16833696
申请日：2016-08-01
发明人： SHIH WEI-YAN , XU XIAOCHEN
CPC分类号： B06B1/0629 , B06B1/0292 , B06B1/0622
摘要： An ultrasonic transducer. The ultrasonic transducer has an interposer having electrical connectivity contacts. The ultrasonic transducer also has an ultrasonic receiver, comprising an array of receiving elements, physically fixed relative to the interposer and coupled to electrically communicate with electrical connectivity contacts of the interposer. The ultrasonic transducer also has at least one ultrasonic transmitter, separate from the ultrasonic receiver, physically fixed relative to the interposer and coupled to electrically communicate with electrical connectivity contacts of the interposer.
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公开(公告)号：EP3198297A4
公开(公告)日：2018-07-25
申请号：EP15822171
申请日：2015-07-17
IPC分类号： G01S7/285 , G01S13/536 , G01S13/87 , G01S13/93
CPC分类号： G01S7/03 , G01S7/352 , G01S13/343 , G01S13/42 , G01S13/87 , G01S13/878 , G01S13/931 , G01S2007/356
摘要： A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.
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公开(公告)号：EP3221956A4
公开(公告)日：2018-07-11
申请号：EP15839652
申请日：2015-09-10
发明人： RANMUTHU INDUMINI W
CPC分类号： H02M3/07 , G05F5/00 , H02M1/08 , H02M1/32 , H02M3/155 , H02M2001/0006 , H03K2217/0063 , H03K2217/0081
摘要： This disclosure describes techniques for controlling a power supply voltage for a high-side gate driver that is used in a power converter. In some examples, in response to an overvoltage condition that occurs on an input voltage lead of a power converter, a power converter may decouple a terminal of a charge pump capacitor from the input voltage lead, and couple the terminal of the capacitor to a reference voltage lead. In further examples, in response to an overvoltage condition that occurs on an input voltage lead of a power converter, a power converter may turn off both switching transistors.
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公开(公告)号：EP3216053A4
公开(公告)日：2018-07-11
申请号：EP15857773
申请日：2015-11-06
IPC分类号： H01L23/485 , H01L21/50 , H01L23/13 , H01L23/14
CPC分类号： H01L23/147 , H01L21/481 , H01L21/4846 , H01L23/13 , H01L23/3738 , H01L24/83 , H01L24/97 , H01L2224/06181 , H01L2224/32225 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/15153 , H01L2924/157
摘要： A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
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公开(公告)号：EP1187028B1
公开(公告)日：2018-07-11
申请号：EP01000436.4
申请日：2001-09-07
IPC分类号： G06F13/364
CPC分类号： G06F13/364 , G06F13/4031
摘要： The immediate grant bus arbiter (300) of this invention is a part in the implementation of a multiple transaction bus system. A b
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公开(公告)号：EP3213602A4
公开(公告)日：2018-07-04
申请号：EP14905035
申请日：2014-10-28
发明人： RUAN CHENJIE , DENG LI
CPC分类号： H05B33/0818 , H05B33/0815 , H05B33/0845 , Y02B20/346
摘要： A light emitting diode (LED) driver includes a first and second switches and control logic. The first switch is configured to switch on and off to regulate a voltage level at an output voltage node. The voltage level at the output voltage node is to power multiple LEDs. The second switch is configured to switch on and off to vary brightness of the LEDs. Based on an external signal, the control logic is configured to control first and second control signals to switch on and off the first and second switches, respectively. Based on an active time portion of the external signal, the control logic concurrently determines an active time portion of the second control signal and a number of switching cycles of the first control signal to switch on and off the first switch.
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公开(公告)号：EP3221999A4
公开(公告)日：2018-06-27
申请号：EP15846625
申请日：2015-09-29
发明人： PICARD JEAN , ABRAMSON DAVID N , JACOBS KARL H
CPC分类号： H05B33/089 , G06F1/266 , H04L12/10 , H04L12/12 , H04L12/40045 , H05B33/0815 , H05B37/0254
摘要： In a Power over Ethernet (PoE) system, a Powered Device (PD) having circuitry to measure the load current from a Power Sourcing Equipment (PSE) in the PD. Circuitry compares the measured load current with a first threshold. Circuitry automatically generates load pulses for signaling the PSE, that power to the PD should be maintained.
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公开(公告)号：EP3192153A4
公开(公告)日：2018-06-27
申请号：EP15818933
申请日：2015-07-10
发明人： KUHN RUEDIGER , GERBER JOHANNES , RUCK BERNHARD , QAIYUM ASIF
IPC分类号： H02K5/22 , G01R19/165 , H03M1/46
CPC分类号： G01R19/16576 , H03M1/1245 , H03M1/46
摘要： A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|
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公开(公告)号：EP3286578A4
公开(公告)日：2018-06-20
申请号：EP16756345
申请日：2016-02-25
CPC分类号： G01S13/02 , G01S7/415 , G01S13/58 , G01S13/584 , G01S2007/356 , G06F3/011 , G06F3/017 , H05K999/99
摘要： A method for operating a frequency modulated continuous wave (FMCW) radar system is provided that includes generating digital intermediate frequency (IF) signals from radio frequency signals received by a small receive antenna array in the FMCW radar system and processing the digital IF signals to determine whether or not a gesture was performed.
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公开(公告)号：EP3304996A4
公开(公告)日：2018-05-30
申请号：EP16804466
申请日：2016-06-02
IPC分类号： H04W72/04
摘要： Excessive latencies and power consumption are avoided when a large number of leaf nodes (LNs) contend simultaneously to join a time slotted channel hopping wireless communication network having a root node (RN) interfaced to LNs by one or more intermediate nodes (INs). A first plurality of shared transmit/receive slots (STRSs) is allocated for at least one IN, and a second plurality of STRSs is advertised for use by contending LNs, where the first plurality is larger than the second plurality. When a LN joins, its STRSs are re-defined such that most become shared transmit-only slots (STOSs) and no STRSs remain. The numbers of STRSs allocated to INs may vary inversely with their hop counts from the RN. One or more STOSs may be added for each of one or more INs in response to a predetermined network condition.
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