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    FPGA with distributed switch matrix
    2.
    发明公开
    FPGA with distributed switch matrix 失效
    FPGA计数器Schaltmatrix。

    公开(公告)号：EP0612153A1

    公开(公告)日：1994-08-24

    申请号：EP94300937.3

    申请日：1994-02-09

    申请人： AT&T Corp.

    发明人： Britton, Barry Kevin ,  Hill, Dwight Douglas ,  Oswald, William Anthony

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17796 ,  H03K19/17704

    摘要： A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors (e.g., 305, 306, 307), referred to as "Switching R-nodes". The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors (e.g., 301, 302, 303, 304) to other selected ones of the (e.g., vertical) routing conductors (e.g., 308, 309, 310, 311, 312). In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.

    摘要翻译： 现场可编程门阵列（FPGA）包括用于可编程地连接各种布线导体的分布式开关矩阵。 分布式交换矩阵包括称为“切换R节点”的附加导体（例如，305,306,307）的组。 交换R节点可编程地将（例如，水平）路由导体（例如，301,302,303,304）中的选定的路由导体连接到（例如，垂直）路由导体（例如，308,309,310）中的其他选定的路由导体 ，311,312）。 以这种方式，可以避免路由导体之间的直接连接，从而允许减少数量的可编程互连设备。 在一个优选实施例中，使用半字节模式架构，其中为每组布线导体提供四条数据导体，其他四分之一数据导体也是有利的。

    Field programmable function element
    3.
    发明公开
    Field programmable function element 失效
    Feldprogrammierbares Funktionselement。

    公开(公告)号：EP0507507A2

    公开(公告)日：1992-10-07

    申请号：EP92302642.1

    申请日：1992-03-26

    申请人： AT&T Corp.

    发明人： Hill, Dwight Douglas

    IPC分类号： H03K19/177 ,  G11C7/00

    CPC分类号： H03K19/1776 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： A field configurable function element offers multi-function use of memory cells by organizing the cells in memory banks and by providing internal configurable interconnections of the memory banks. A versatile logic function configuration is obtained by storing the truth table of the desired logic functions in the memory cells. An arithmetic functions configuration is obtained by internally interconnecting the memory cells. A read/write memory function configuration is obtained by adding write address decoding, write enablement capability and input data leads. The configuration permits a parallel writing and reading of the memory cells, thereby effectuating a two- port memory operation. An added set of latches connected to the configurable function element and a configurable routing network connected to the inputs of the configurable function element, to the output of the configurable function element and to the output of the latches, form a powerful device that can be easily configured to any one of the three primary modes (logic, arithmetic and memory). A generalized routing fabric coupled to the routing network provides for configurable connections to other configurable function devices. To minimize the load that such a device may present to the routing fabric because of the various configurable interconnections that it can effect, the input leads from the routing fabric to the routing network in configurable function device are all multiplexed to one, or a few contact points, via an intermediate level of routing.

    摘要翻译： 现场可配置功能元件通过组织存储体中的单元并且通过提供存储体的内部可配置互连来提供存储器单元的多功能使用。 通过将期望的逻辑功能的真值表存储在存储器单元中来获得通用的逻辑功能配置。 通过内部互连存储器单元获得算术功能配置。 通过添加写入地址解码，写入使能能力和输入数据引线来获得读/写存储器功能配置。 该配置允许对存储器单元的并行写入和读取，从而实现双端口存储器操作。 连接到可配置功能元件的附加的锁存器和连接到可配置功能元件的输入到可配置功能元件的输出和锁存器的输出的可配置路由网络形成可以容易地实现的强大的设备 配置为三种主要模式（逻辑，算术和存储器）中的任何一种。 耦合到路由网络的通用路由结构提供到其他可配置功能设备的可配置连接。 为了最小化这样的设备可能由于其可以影响的各种可配置互连而呈现给路由结构的负载，从可配置功能设备中的路由结构到路由网络的输入引脚都被复用到一个或几个接触 点，通过中间级别的路由。

    Field programmable gate array with direct input/output connection
    4.
    发明公开
    Field programmable gate array with direct input/output connection 失效
    具有直接输入/输出连接的现场可编程门阵列。

    公开(公告)号：EP0617513A3

    公开(公告)日：1996-02-28

    申请号：EP94301900.0

    申请日：1994-03-16

    申请人： AT&T Corp.

    发明人： Britton, Barry Kevin ,  Oswald, William Anthony ,  Hill, Dwight Douglas

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17744 ,  H03K19/1736

    摘要： A field programmable gate array includes a dedicated path (606) which directly connects an I/O pad (604) to a selected register (603) in the array of programmable function units (602). For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver (605), to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may also be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.

    Multiple voltage supplies for field programmable gate arrays and the like
    5.
    发明公开
    Multiple voltage supplies for field programmable gate arrays and the like 失效
    多个电源为现场可编程门阵列和这种门阵列。

    公开(公告)号：EP0544461A2

    公开(公告)日：1993-06-02

    申请号：EP92310580.3

    申请日：1992-11-19

    申请人： AT&T Corp.

    发明人： Hill, Dwight Douglas

    IPC分类号： G11C11/417

    CPC分类号： G11C11/419 ,  G11C11/417

    摘要： A field programmable array of application circuitry (C1,C2,...) is programmed (or reprogrammed) by first applying application circuitry power supply (AV dd =5v) to the application circuitry, and then applying a binary digital data signal (D0/D1) through the source-drain path of an access transistor (N3) in its on condition to the SRAM that controls the on/off condition of its associated controlled pass transistor (N4). This SRAM is one of a row-column array of similar SRAMs, and the access transistors for all SRAMs on the same row are similarly supplied with data signals through access transistors. The pass transistor determines whether application circuitry interconnection points (A1,A2), are going to be connected after the programming (or reprogramming) is terminated. While the data signal (D0/D1) is applied to the SRAM, and the power supply (PV DD ) for the SRAM is maintained at an intermediate level (3v) below the level of the application circuitry power supply voltage (AV dd =5v) and below the high binary level (D1), a row-select pulse (S) is applied to a control terminal of the access transistor, as well as to all control terminals of access transistors for accessing all other SRAMs on the same row. The row-select pulse (S) is then terminated and the SRAMs on other rows (if need be) are similarly written (or re-written). Then the power supply (PV DD ) for the SRAMs is increased to a level (PV DD =6v) advantageously higher, by a threshold of the pass transistor (N4), than that of the application circuitry (AV dd =5v), to reduce both voltage drops and power losses in pass transistors.

    摘要翻译： 应用电路的现场可编程阵列（C1，C2，...）是通过首先将应用电路的电源（AVDD = 5V）到应用电路，然后施加一个二进制数字数据信号（D0 /编程（或重新编程） D1）通过在（一个存取晶体管（L3）的源 - 漏通路的条件到SRAM那样控制其相关联的控制的传输晶体管N4）的开/关状态。 此SRAM是类似的SRAM的一个行 - 列阵列的一个，并为所有在同一行中的存取晶体管的SRAM被类似地与数据信号通过存取晶体管提供。 bestimmt无论应用电路互连点（A1，A2）要编程（或重新编程）后要连接的传输晶体管被终止。 虽然数据信号（D0 / D1）被施加到SRAM和SRAM的电源（PVDD）维持在低于应用电路的电源电压的电平的中间电平（3V）（AVDD = 5V）和 以下的高二进制电平（D1），一个行选择脉冲（S）施加到所述存取晶体管的控制端，以及到存取晶体管的全部控制端子，用于访问在同一行上的所有其它的SRAM。 然后，将行选择脉冲（S）被终止，并且在其它行所述SRAMs（如果需要的话）被类似地写（或重写）。 然后SRAM的电源（PVDD）增加到一个水平（PVDD = 6V）有利地更高，通过传输晶体管（N4）比应用电路（AVDD = 5V）的阈值，以降低这两种电压 滴和在传输晶体管的功率损耗。

    Multiple voltage supplies for field programmable gate arrays and the like
    7.
    发明公开
    Multiple voltage supplies for field programmable gate arrays and the like 失效
    用于现场可编程门阵列的多电压电源等

    公开(公告)号：EP0544461A3

    公开(公告)日：1994-02-02

    申请号：EP92310580.3

    申请日：1992-11-19

    申请人： AT&T Corp.

    发明人： Hill, Dwight Douglas

    IPC分类号： G11C11/417

    CPC分类号： G11C11/419 ,  G11C11/417

    摘要： A field programmable array of application circuitry (C1,C2,...) is programmed (or reprogrammed) by first applying application circuitry power supply (AV dd =5v) to the application circuitry, and then applying a binary digital data signal (D0/D1) through the source-drain path of an access transistor (N3) in its on condition to the SRAM that controls the on/off condition of its associated controlled pass transistor (N4). This SRAM is one of a row-column array of similar SRAMs, and the access transistors for all SRAMs on the same row are similarly supplied with data signals through access transistors. The pass transistor determines whether application circuitry interconnection points (A1,A2), are going to be connected after the programming (or reprogramming) is terminated. While the data signal (D0/D1) is applied to the SRAM, and the power supply (PV DD ) for the SRAM is maintained at an intermediate level (3v) below the level of the application circuitry power supply voltage (AV dd =5v) and below the high binary level (D1), a row-select pulse (S) is applied to a control terminal of the access transistor, as well as to all control terminals of access transistors for accessing all other SRAMs on the same row. The row-select pulse (S) is then terminated and the SRAMs on other rows (if need be) are similarly written (or re-written). Then the power supply (PV DD ) for the SRAMs is increased to a level (PV DD =6v) advantageously higher, by a threshold of the pass transistor (N4), than that of the application circuitry (AV dd =5v), to reduce both voltage drops and power losses in pass transistors.

    摘要翻译： 通过首先将应用电路电源（AVdd = 5v）施加到应用电路，然后将二进制数字数据信号（D0 / D2）施加到应用电路（C1，C2，...）来编程（或重新编程） D1）通过处于导通状态的存取晶体管（N3）的源极 - 漏极路径与控制其相关的受控制通过晶体管（N4）的导通/截止条件的SRAM。 该SRAM是类似SRAM的行列阵列之一，并且用于同一行上的所有SRAM的存取晶体管类似地通过存取晶体管被提供数据信号。 传输晶体管确定应用电路互连点（A1，A2）是否在编程（或重新编程）终止之后连接。 当数据信号（D0 / D1）施加到SRAM时，SRAM的电源（PVDD）保持在低于应用电路电源电压（AVdd = 5v）的中间电平（3v）以及 在高二进制电平（D1）之下，行选择脉冲（S）被施加到存取晶体管的控制端子，以及存取晶体管的所有控制端子以访问同一行上的所有其他SRAM。 行选择脉冲（S）终止，其他行上的SRAM（如果需要的话）被类似地写入（或重写）。 然后，将SRAM的电源（PVDD）增加到比传输晶体管（N4）的阈值高的电平（PVDD = 6v），以比应用电路的电源（AVdd = 5v）更高，以降低电压 传输晶体管中的电压降和功率损耗。

    Field programmable function element
    8.
    发明公开
    Field programmable function element 失效
    现场可编程功能元件

    公开(公告)号：EP0507507A3

    公开(公告)日：1993-02-24

    申请号：EP92302642.1

    申请日：1992-03-26

    申请人： AT&T Corp.

    发明人： Hill, Dwight Douglas

    IPC分类号： H03K19/177 ,  G11C7/00

    CPC分类号： H03K19/1776 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： A field configurable function element offers multi-function use of memory cells by organizing the cells in memory banks and by providing internal configurable interconnections of the memory banks. A versatile logic function configuration is obtained by storing the truth table of the desired logic functions in the memory cells. An arithmetic functions configuration is obtained by internally interconnecting the memory cells. A read/write memory function configuration is obtained by adding write address decoding, write enablement capability and input data leads. The configuration permits a parallel writing and reading of the memory cells, thereby effectuating a two- port memory operation. An added set of latches connected to the configurable function element and a configurable routing network connected to the inputs of the configurable function element, to the output of the configurable function element and to the output of the latches, form a powerful device that can be easily configured to any one of the three primary modes (logic, arithmetic and memory). A generalized routing fabric coupled to the routing network provides for configurable connections to other configurable function devices. To minimize the load that such a device may present to the routing fabric because of the various configurable interconnections that it can effect, the input leads from the routing fabric to the routing network in configurable function device are all multiplexed to one, or a few contact points, via an intermediate level of routing.

    Field programmable gate array with direct input/output connection
    10.
    发明公开
    Field programmable gate array with direct input/output connection 失效
    程序员Gastanordnung mit direkter Eingangs- / Ausgangsverbindung。

    公开(公告)号：EP0617513A2

    公开(公告)日：1994-09-28

    申请号：EP94301900.0

    申请日：1994-03-16

    申请人： AT&T Corp.

    发明人： Britton, Barry Kevin ,  Oswald, William Anthony ,  Hill, Dwight Douglas

    IPC分类号： H03K19/177 ,  H03K19/173

    CPC分类号： H03K19/17744 ,  H03K19/1736

    摘要： A field programmable gate array includes a dedicated path (606) which directly connects an I/O pad (604) to a selected register (603) in the array of programmable function units (602). For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver (605), to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may also be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.

    摘要翻译： 包括现场可编程门阵列的整合电路包括多个可编程逻辑单元，其包括至少一个可编程功能单元，该至少一个可编程功能单元包括从由组合逻辑和顺序逻辑组成的组中选择的至少一个逻辑元件，并且还包括相关联的路由资源，包括 路由导体和可配置互连点，以及多个可编程输入/输出单元，包括从由输入驱动器和输出驱动器组成的组中选择的至少一个驱动器，并且还包括一个或多个相关联的焊盘。 现场可编程门阵列还包括给定可编程功能单元中的给定逻辑元件的输入或输出之间的直接路径，以及分配给给定可编程输入/输出中的输入驱动器或输出驱动器 细胞。