公开(公告)号：EP0493876B1

公开(公告)日：1998-08-05

申请号：EP91309728.3

申请日：1991-10-22

申请人： AT&T Corp.

发明人： Segelken, John Maurice ,  Shively, Richard Robert ,  Stanziola, Christopher Anthony ,  Wu, Lesley Jen-Yuan

IPC分类号： G06F15/16 ,  G06F15/80

CPC分类号： G06F17/5068 ,  H05K7/023

公开(公告)号：EP0478121A3

公开(公告)日：1992-04-15

申请号：EP91306586.8

申请日：1991-07-19

申请人： AT&T Corp.

发明人： Segelken, John Maurice ,  Shively, Richard Robert ,  Stanziola, Christopher Anthony ,  Wu, Lesley Jen-Yuan

IPC分类号： G06F13/40 ,  H05K7/02

CPC分类号： H05K7/023 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/144 ,  H01L2924/00014

摘要： A system is described for arraying multi-device processing nodes (1,2) in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a static RAM, and a communications and network controller. The nodes or tiles are 4-connected, each having logical north, east, south and west ports. The nodes are mounted on boards (17,18,19). Selective connection of essentially any one port to another on a different board is effected by use of a routing and spacer element (50) having internal routing paths preselected to support a desired node interconnection architecture. Novel multiprocessing architectures and connections to a Host computer are also disclosed.

公开(公告)号：EP0493876A3

公开(公告)日：1994-05-18

申请号：EP91309728.3

申请日：1991-10-22

申请人： AT&T Corp.

发明人： Segelken, John Maurice ,  Shively, Richard Robert ,  Stanziola, Christopher Anthony ,  Wu, Lesley Jen-Yuan

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F15/60

CPC分类号： G06F17/5068 ,  H05K7/023

摘要： The number of circuit path crossover points on boards (10) mounting plural connected multichip modules (5 to 8) is substantially reduced over the number that would otherwise be required. For 4-sided modules and boards, the modules are arranged on the board in such a way that their inter-connecting north-east-south-west ports are successively reordered to N-S-E-W. Additionally, further advantage in reducing crossover vias may be gained by combining the reordering with a phased rotation of the modules from their nominal congruent board position. For the 4-sided module, these expedients virtually eliminate crossover vias between the east and west ports. It also provides for all multi-chip modules a ready common bus structure (66,69) located at a common interior area of the mounting board, to which the E and W-ports are oriented. The invention is applicable to a class of multi-sided, multi-chip modules on boards with alike number of sides.

公开(公告)号：EP0493876A2

公开(公告)日：1992-07-08

申请号：EP91309728.3

申请日：1991-10-22

申请人： AT&T Corp.

发明人： Segelken, John Maurice ,  Shively, Richard Robert ,  Stanziola, Christopher Anthony ,  Wu, Lesley Jen-Yuan

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F15/60

CPC分类号： G06F17/5068 ,  H05K7/023

摘要： The number of circuit path crossover points on boards (10) mounting plural connected multichip modules (5 to 8) is substantially reduced over the number that would otherwise be required. For 4-sided modules and boards, the modules are arranged on the board in such a way that their inter-connecting north-east-south-west ports are successively reordered to N-S-E-W. Additionally, further advantage in reducing crossover vias may be gained by combining the reordering with a phased rotation of the modules from their nominal congruent board position. For the 4-sided module, these expedients virtually eliminate crossover vias between the east and west ports. It also provides for all multi-chip modules a ready common bus structure (66,69) located at a common interior area of the mounting board, to which the E and W-ports are oriented. The invention is applicable to a class of multi-sided, multi-chip modules on boards with alike number of sides.

摘要翻译： 安装多个连接的多芯片模块（5至8）的电路板（10）上的电路路径交叉点的数量大大减少了否则将需要的数量。 对于四面模块和单板，模块布置在板上，使其相互连接的东北 - 西南端口依次重新排列到N-S-E-W。 此外，通过将重新排序与其标称的一致的板位置的模块的相位旋转组合可以获得减少交叉通孔的进一步的优点。 对于四面模块，这些功能实际上可以消除东西端口之间的交叉通孔。 它还为所有多芯片模块提供位于安装板的公共内部区域的准备好的公共总线结构（66,69），E和W端口定向到该安装板。 本发明适用于具有相同数量侧面的板上的一类多边多芯片模块。

公开(公告)号：EP0478121B1

公开(公告)日：1997-10-08

申请号：EP91306586.8

申请日：1991-07-19

申请人： AT&T Corp.

发明人： Segelken, John Maurice ,  Shively, Richard Robert ,  Stanziola, Christopher Anthony ,  Wu, Lesley Jen-Yuan

IPC分类号： G06F13/40 ,  H05K7/02

CPC分类号： H05K7/023 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/144 ,  H01L2924/00014

公开(公告)号：EP0478121A2

公开(公告)日：1992-04-01

申请号：EP91306586.8

申请日：1991-07-19

申请人： AT&T Corp.

发明人： Segelken, John Maurice ,  Shively, Richard Robert ,  Stanziola, Christopher Anthony ,  Wu, Lesley Jen-Yuan

IPC分类号： G06F13/40 ,  H05K7/02

CPC分类号： H05K7/023 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K1/144 ,  H01L2924/00014

摘要： A system is described for arraying multi-device processing nodes (1,2) in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a static RAM, and a communications and network controller. The nodes or tiles are 4-connected, each having logical north, east, south and west ports. The nodes are mounted on boards (17,18,19). Selective connection of essentially any one port to another on a different board is effected by use of a routing and spacer element (50) having internal routing paths preselected to support a desired node interconnection architecture. Novel multiprocessing architectures and connections to a Host computer are also disclosed.

摘要翻译： 描述了用于在三维计算架构中排列多设备处理节点（1,2）并且用于灵活地连接其端口的系统。 每个处理节点的拓扑结构具有固定和恒定的物理几何。 节点可以包括数字信号处理器芯片，静态RAM以及通信和网络控制器。 节点或瓦片是4连接的，每个节点或瓦片具有逻辑的北，东，南和西端口。 节点安装在板（17,18,19）上。 通过使用具有预选的支持所需节点互连体系结构的内部路由路径的路由和间隔元件（50）来实现基本上任何一个端口到另一板上的不同板上的选择性连接。 还公开了新的多处理架构和与主机的连接。