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1.发明授权Verfahren und Vorrichtung zum Herstellen dünner epitaktischer Halbleiterschichten 有权方法和装置用于制造薄的外延半导体层
公开(公告)号：EP1415332B1
公开(公告)日：2012-01-25
申请号：EP02779254.8
申请日：2002-07-25
IPC分类号： H01L21/20 , H01L21/205 , C23C16/32 , C23C16/54
CPC分类号： H01L21/02529 , C23C16/0218 , C23C16/54 , H01L21/02532 , H01L21/0262 , H01L21/02658
摘要： The invention relates to a method and devices for the production of diffusion-inhibiting epitactic semiconductor layers. The aim of the invention is to provide a method and devices which are used to produce thin diffusion-inhibiting epitactic semiconductor layers on large substrates commonly used in semiconductor engineering at a high industrial manufacturing throughput rate for typical HBT stacks. According to the invention, the surfaces of the semiconductor substrates to be coated are initially cleaned. The cleaned semiconductor substrates are then heated to a first temperature (pre-bake temperature), which is higher than the temperature of the subsequent step, in a low-pressure batch reactor and the surfaces to be coated undergo a hydrogen pre-bake process at a lower, same or higher reactor pressure in comparison with the subsequent procedural step in order to remove air oxide and other impurities. In the next step, the pre-treated semiconductor substrates are heated to a second temperature which is lower in comparison with the previous procedural step (deposition temperature) in a low pressure, hot or warm wall batch reactor. Once a thermodynamic balance is achieved for the surfaces to be coated, the diffusion-inhibiting semiconductor layers are deposited in a chemical deposition process (CVD) at a reactor pressure which is higher, the same as or lower than that of the previous procedural step.
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2.发明公开METHOD FOR PREVENTING VERTICAL AND LATERAL INHOMOGENEITIES WHEN ETCHING THROUGH-SILICON VIAS 审中-公开通过硅通孔蚀刻时预防垂直和横向不均匀性的方法
公开(公告)号：EP3306654A1
公开(公告)日：2018-04-11
申请号：EP17193221.3
申请日：2017-09-26
发明人： WIETSTRUCK, Matthias , KAYNAK, Mehmet , KULSE, Philip , LISKER, Marco , MARSCHMEYER, Steffen , WOLANSKY, Dirk
IPC分类号： H01L21/768 , H01L23/48
摘要： A method for producing a semiconductor device, comprising the steps of: providing a silicon wafer having a plurality of raised portions of equal height on a first surface of the silicon wafer as a placeholder for through-silicon vias; depositing an etch stop layer on the first surface of the silicon wafer; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the surface of the etch stop layer; producing components on or in a second surface of the silicon wafer in a front-end-of-line process; etching a plurality of trenches into the silicon wafer using a masked etching process, proceeding from the second surface of the silicon wafer, each trench being formed at the respective location of one raised portion of the plurality of raised portions; depositing side wall insulation layers made of insulating material on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a back-end-of-line process for contacting the active components on the second surface of the silicon wafer; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the through-silicon vias by partially removing the etch stop layer.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在硅晶片的第一表面上提供具有相同高度的多个凸起部分的硅晶片作为硅通孔的占位符; 在硅晶片的第一表面上沉积蚀刻停止层; 平坦化蚀刻停止层的表面; 将第一载体晶片永久地结合在所述蚀刻停止层的表面上; 在线前处理中在硅晶片的第二表面上或其中生产组件; 使用掩模蚀刻工艺将多个沟槽蚀刻到硅晶片中，从硅晶片的第二表面开始，每个沟槽形成在多个凸起部分的一个凸起部分的相应位置处; 在沟槽的侧壁上沉积由绝缘材料制成的侧壁绝缘层; 通过用导电材料填充沟槽来形成硅通孔; 在后端处理工艺中产生导体路径堆叠，用于接触硅晶片的第二表面上的有源部件; 将第二载体晶片暂时接合到所述导体路径堆叠的表面上; 通过部分地去除所述蚀刻停止层来去除所述第一载体晶片并且暴露所述硅通孔。
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公开(公告)号：EP3306654B1
公开(公告)日：2019-11-06
申请号：EP17193221.3
申请日：2017-09-26
发明人： WIETSTRUCK, Matthias , KAYNAK, Mehmet , KULSE, Philip , LISKER, Marco , MARSCHMEYER, Steffen , WOLANSKY, Dirk
IPC分类号： H01L21/768 , H01L23/48
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公开(公告)号：EP1118124B1
公开(公告)日：2010-12-01
申请号：EP99955791.1
申请日：1999-09-20
IPC分类号： H01L29/732 , H01L21/331
CPC分类号： H01L29/66287 , H01L29/7322
摘要： The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide highly conductive connections between the metal contacts and the active (internal) transistor region and a minimized passive transistor surface while at the same time avoiding greater process complexity and increased contact resistances. To this end, by creating suitable epitaxis conditions a poly-silicon layer is deposited on the insulating area which is thicker than the epitaxis layer in the active transistor area. The greater thickness of the poly-silicon layer in relation to the epitaxis layer is achieved through the use of a very low temperature for the deposition of part or all of the buffer layer. Th use of a very low deposition temperature results in improved seeding of the insulating layer and a reduction in the deposition dead time, which makes it possible to produce a thicker layer on the insulating layer than in the active transistor area.
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