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    Improved multiprocessor system
    3.
    发明公开
    Improved multiprocessor system 失效
    Multiprozessorsystem。

    公开(公告)号：EP0404560A2

    公开(公告)日：1990-12-27

    申请号：EP90306777.5

    申请日：1990-06-21

    申请人： KENDALL SQUARE RESEARCH CORPORATION

    发明人： Frank, Steven J. ,  Burkhardt, Henry, III ,  Rothnie, James B. ,  Margulies, Benson I. ,  Weber, Frederick D. ,  Lee, Linda Q.

    IPC分类号： G06F15/16 ,  G06F12/08

    CPC分类号： G06F9/3865 ,  G06F11/004 ,  G06F15/17337

    摘要： A digital data processing system includes a plurality of central processor units (40A, 40B, 40C) which share and access a common memory (44A, 44B, 44C) through a memory management element (46) . The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all central processing units requesting access to a given datum residing in memory are signalled of the datums existence. In the second mode, only selected central processing units requesting access to a resident datum are notified that it exists, while others requesting access to the datum are signalled that it does not exist. The common memory can include a plurality of independent memory elements (44A, 44B, 44C) each coupled to and associated with, a respective one of the central processing units. A central processing unit can include a post-store element for effecting the transfer of copies of data stored in its associated memory element to a memory element associated with another central processing unit.

    摘要翻译： 数字数据处理系统包括通过存储器管理元件（46）共享和访问公共存储器（44A，44B，44C）的多个中央处理器单元（40A，40B，40C）。 存储器管理元件尤其允许以至少两种模式访问公共存储器中的数据。 在第一模式中，请求访问驻留在存储器中的给定数据的所有中央处理单元用信号表示基准存在。 在第二模式中，只有请求访问驻留数据的所选择的中央处理单元被通知其存在，而请求访问基准的其他中央处理单元被发信号通知其不存在。 公共存储器可以包括多个独立存储器元件（44A，44B，44C），每个独立存储器元件耦合到相应的一个中央处理单元并与之相关联。 中央处理单元可以包括用于实现将存储在其关联的存储器元件中的数据的副本传送到与另一中央处理单元相关联的存储元件的后存储元件。

    Interconnect system for multiprocessor structure
    7.
    发明公开
    Interconnect system for multiprocessor structure 失效
    多处理器结构互连系统

    公开(公告)号：EP0322116A3

    公开(公告)日：1990-08-08

    申请号：EP88311138.7

    申请日：1988-11-24

    申请人： KENDALL SQUARE RESEARCH CORPORATION

    发明人： Frank, Steven J. ,  Burkhardt Henry III ,  Weber, Frederick D.

    IPC分类号： G06F15/06 ,  G06F15/16 ,  H04L12/42

    CPC分类号： G06F15/17337 ,  H04L12/433

    摘要： An improved digital data processing apparatus has a plurality of processing cells, at least one of which includes a central processing unit (2), an associated memory element (2), and a cell interconnect element (12). The processing cells are coupled in a ring configuration on a bus which includes a shift register element having a set of digital storage and transfer stages connected in series. These stages sequentially store and transfer digital signals applied to the bus. The cell interconnect element is arranged for sending digital signals on the bus by way of the shift register.

    Interconnect system for multiprocessor structure
    9.
    发明公开
    Interconnect system for multiprocessor structure 失效
    ZwischenverbindungssystemfürMultiprozessorstruktur。

    公开(公告)号：EP0322116A2

    公开(公告)日：1989-06-28

    申请号：EP88311138.7

    申请日：1988-11-24

    申请人： KENDALL SQUARE RESEARCH CORPORATION

    发明人： Frank, Steven J. ,  Burkhardt Henry III ,  Weber, Frederick D.

    IPC分类号： G06F15/06 ,  G06F15/16 ,  H04L12/42

    CPC分类号： G06F15/17337 ,  H04L12/433

    摘要： An improved digital data processing apparatus has a plurality of processing cells, at least one of which includes a central processing unit (2), an associated memory element (2), and a cell interconnect element (12). The processing cells are coupled in a ring configuration on a bus which includes a shift register element having a set of digital storage and transfer stages connected in series. These stages sequentially store and transfer digital signals applied to the bus. The cell interconnect element is arranged for sending digital signals on the bus by way of the shift register.

    摘要翻译： 改进的数字数据处理装置具有多个处理单元，其中至少一个包括中央处理单元（2），相关的存储元件（2）和单元互连元件（12）。 处理单元以环形配置耦合在总线上，该总线包括具有串联连接的一组数字存储和传输级的移位寄存器元件。 这些级顺序存储和传送应用于总线的数字信号。 单元互连元件被布置用于通过移位寄存器在总线上发送数字信号。