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公开(公告)号：EP2033317A1
公开(公告)日：2009-03-11
申请号：EP07799075.2
申请日：2007-06-27
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K23/00
CPC分类号： H03K23/54
摘要： A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also receives a feedback modulus control signal from another MDS. When in the divide-by-two mode, the MDS divides by two regardless of the feedback modulus control signal. To conserve power, the first stage is unpowered when the MDS stage operates in the divide-by-two mode. When in the divide-by-three mode, the MDS stage either divides by two or by three depending on the feedback modulus control signal. To further reduce power consumption, the first stage is unpowered when the MDS stage is in the divide-by-three mode but is nonetheless performing a divide-by-two operation. A power-down transistor holds the output of the first stage at the proper logic level when the first stage is unpowered.
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公开(公告)号：EP2883305A1
公开(公告)日：2015-06-17
申请号：EP13750611.9
申请日：2013-08-08
摘要： Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.
摘要翻译： 用于为多级共源共栅放大器生成偏置电压的技术。 在一个方面中，提供了多级共射共基放大器偏置网络，偏置网络中的每个晶体管是多级共射共基放大器中的对应晶体管的复制品，其实现了多级共射共基放大器中的晶体管的精确偏置。 在进一步的方面中，用于多级共射共基放大器的电压供应与用于复制品偏置网络的电压供应分离地提供，以有利地将放大器电压供应中的变化与偏置网络电压供应去耦。 在又一方面，多级共射共基放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。 由于放大器的增益取决于共源共栅放大器的偏置电压，所以放大器的增益可以以这种方式有利地被调整，而不会直接在放大器信号路径中引入可变增益元件。
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公开(公告)号：EP2340612A1
公开(公告)日：2011-07-06
申请号：EP09767874.2
申请日：2009-06-19
CPC分类号： H03F1/3276 , H03F1/301 , H03F1/308 , H03F1/3241 , H03F3/245 , H03F3/3022 , H03F2200/336 , H03F2200/451 , H03F2200/453 , H03F2203/30099 , H03F2203/30132 , H03F2203/7231
摘要： Techniques are disclosed for extending an amplifier's linear operating range by concatenating an amplifier exhibiting gain compression with a gain expansion stage. In an exemplary embodiment, a gain expansion stage incorporates a Class-B stage, a Class-AB stage, or a combination of the two. In an exemplary embodiment, both the gain compression stage and gain expansion stage are provided with a replica current biasing scheme to ensure stable biasing current over variations in temperature, process, and/or supply voltage. Further disclosed is an output voltage biasing scheme to set the DC output voltage to ensure maximum linear operating range.
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4.发明公开CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开TAKT- UND DATENTREIBER MITERHÖHTERTRANSKONDUKTANZ UNDUNTERDRÜCKTEMGLEICHTAKTBEREICH
公开(公告)号：EP3066756A1
公开(公告)日：2016-09-14
申请号：EP14859633.1
申请日：2014-11-05
发明人： SU, Wenjun , YIN, Guangming , ZHU, Quanqing
IPC分类号： H03K5/12
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译： 提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。 一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动放大器，一对n级电路和输入偏斜平均电路，其中， n级单元分为两个半块。 输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极 - 源极电压的偏斜。 对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和操作速度。
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公开(公告)号：EP2467937A1
公开(公告)日：2012-06-27
申请号：EP10747377.9
申请日：2010-08-19
CPC分类号： H03F1/52 , H03F3/24 , H03F2200/435 , H03F2200/78 , H03G3/3042 , H04B2001/0408
摘要： Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes a PA module (310) to amplify an input RF signal and provide an output RF signal and a protection circuit (320) to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit (329) includes a set of comparators (370) to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.
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公开(公告)号：EP2047600A2
公开(公告)日：2009-04-15
申请号：EP07799793.0
申请日：2007-07-24
发明人： NARATHONG, Chiewcharn , SU, Wenjun
CPC分类号： H03K23/667 , H03K21/10 , H03L7/1976
摘要： A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal.
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公开(公告)号：EP2039003B1
公开(公告)日：2018-04-04
申请号：EP07798718.8
申请日：2007-06-18
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K3/356 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01721 , H03K3/356017 , H03K19/018514
摘要： Differential signal output nodes of a novel CML buffer are DC-coupled by contiguous conductors to the differential signal input nodes of a load (for example, a CML logic element). The CML buffer includes a pulldown load latch that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load, thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.
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公开(公告)号：EP2470918B1
公开(公告)日：2018-01-17
申请号：EP10751748.4
申请日：2010-08-27
IPC分类号： G01R19/04
CPC分类号： G01R19/04
摘要： A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.
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公开(公告)号：EP3146622A1
公开(公告)日：2017-03-29
申请号：EP14892709.8
申请日：2014-05-23
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译： 前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。 在一些方面，前馈偏置电路通过在不同的拐角条件下产生不同的偏置信号来补偿电路中的晶体管工艺角。 在一些实现中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。
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公开(公告)号：EP2039003A2
公开(公告)日：2009-03-25
申请号：EP07798718.8
申请日：2007-06-18
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K3/356 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01721 , H03K3/356017 , H03K19/018514
摘要： Differential signal output nodes of a novel CML buffer are DC-coupled by contiguous conductors to the differential signal input nodes of a load (for example, a CML logic element). The CML buffer includes a pulldown load latch that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load, thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.
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