公开(公告)号：EP1665358A2

公开(公告)日：2006-06-07

申请号：EP04788636.1

申请日：2004-09-09

申请人： The Regents of the University of California ,  CREE, INC.

发明人： CHINI, Alessandro ,  MISHRA, Umesh, K. ,  PARIKH, Primit ,  WU, Yifeng

IPC分类号： H01L21/338 ,  H01L31/072 ,  H01L27/095 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/785

摘要： A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.