摘要:
New Group III nitride based field effect transistors (10) and high electron mobility transistors (30) are disclosed that provide enhanced high frequency response characteristics. The preferred transistors (10, 30) are made from GaN/AlGaN and have a dielectric layer (22, 44) on the surface of their barrier layer (18, 38). The dielectric layer (22, 44) has a high percentage of donor electrons (68) that neutralize traps (69) in the barrier layer (18, 38) such that the traps (69) cannot slow the high frequency response of the transistors (10, 30). A new method of manufacturing the transistors (10, 30) is also disclosed, with the new method using sputtering to deposit the dielectric layer (18, 38).
摘要:
A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
摘要:
Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (VDS) of about 56 volts, a gate to source voltage (Vgs) of from about -8 to about -14 volts and a temperature of about 140 °C for at least about 10 hours.
摘要:
A transistor (10) comprises an active region (18) having a channel and source (20) and drain (22) electrodes in contact with the active region. A gate (24, 124,142) is between the source and drain electrodes and on the active region. A plurality of field plates (30,42) is arranged on the active region, each extending toward the drain electrode, and each of which is isolated from the active region and from the others of the field plates. The topmost (42) of the field plates electrically is connected to the source electrode.
摘要:
An LED package containing integrated circuitry for matching a power source voltage to the LED operating voltage, LEDs containing such integrated circuitry, systems containing such packages, and methods for matching the source and operating voltages are described. The integrated circuitry typically contains a power converter and a constant current circuit. The LED package may also contain other active or passive components such as pin-outs for integrated or external components, a transformer and rectifier, or a rectifier circuit. External components can include control systems for regulating the LED current level or the properties of light emitted by the LED. Integrating the power supply and current control components into the LED can provide for fabrication of relatively small LEDs using fewer and less device-specific components.
摘要:
A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it.; An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals. The present invention is particularly applicable to Group III nitride based active semiconductor devices grown on SiC substrates. The passive components and interconnects can then be formed on a lower cost, higher diameter wafer made of GaAs or Si. After separation, the Group III devices can be flip-chip mounted on the GaAs or Si substrate.