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1.发明授权A METHOD AND AN APPARATUS FOR PROVIDING TIMING SIGNALS TO A NUMBER OF CIRCUITS, AN INTEGRATED CIRCUIT AND A NODE 有权方法和一种用于提供定时信号为CIRCUITS集成电路和结一次NUMBER
公开(公告)号：EP1891497B1
公开(公告)日：2017-04-19
申请号：EP06722960.9
申请日：2006-05-26
申请人： Teklatech A/S
发明人： BJERREGAARD, Tobias
IPC分类号： G06F1/10
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公开(公告)号：EP3030945B1
公开(公告)日：2016-12-14
申请号：EP14758010.4
申请日：2014-08-05
申请人： Raytheon Company
IPC分类号： G06F1/10 , H04B10/2575
CPC分类号： H04B10/2575 , G06F1/105 , H04B10/25 , H04B10/2507
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3.发明授权Method and apparatus for coordinating memory operations among diversely-located memory components 有权用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2849075B1
公开(公告)日：2016-10-19
申请号：EP14196752.1
申请日：2002-04-23
申请人： Rambus Inc.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.
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4.发明授权Method and apparatus for coordinating memory operations among diversely-located memory components 有权用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2275943B1
公开(公告)日：2015-03-11
申请号：EP10179117.6
申请日：2002-04-23
申请人： Rambus Inc.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A specific address and control bus, and a data bus (108), are connected to a memory controller (102) and a memory module (103). The data bus using differential signaling, has symbol time lesser than specific address and control bus symbol time.
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5.发明公开
公开(公告)号：EP0588746A1
公开(公告)日：1994-03-23
申请号：EP93480119.2
申请日：1993-08-24
CPC分类号： H04B10/801 , G06F1/105
摘要： A method of clocking integrated circuit chips. A pulsed laser (16) striking an integrated circuit module substrate (14) is diffused through the substrate and exits the opposite surface as diffused light pulses. An integrated circuit chip (10) mounted on the top surface of the substrate has at least one optical receiver (17). The optical receiver receives the pulsed energy from the diffused light pulses, converting them to electrical pulses that clock the chip.
摘要翻译： 集成电路芯片时钟的方法。 撞击集成电路模块衬底（14）的脉冲激光（16）通过衬底扩散并作为漫射光脉冲离开相对表面。 安装在基板的顶表面上的集成电路芯片（10）具有至少一个光接收器（17）。 光接收器从扩散的光脉冲接收脉冲能量，将其转换成对芯片进行时钟的电脉冲。
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公开(公告)号：EP3062454A1
公开(公告)日：2016-08-31
申请号：EP16155581.8
申请日：2016-02-12
发明人： POLSTER, Robert
CPC分类号： H04Q11/0005 , G06F1/105 , H04B10/6911 , H04L7/0008 , H04L7/0075 , H04Q2011/0035 , H04Q2011/0039
摘要： The invention concerns an optical receiver of an optical link having: a photodiode (202) coupled between a detection node (204) and a first supply voltage rail (GND), the photodiode being adapted to receive an optical clock signal including pulses; a switch (206) coupled between the detection node (204) and a second supply voltage rail (VDD); and a first transistor (211) coupled by its main conducting nodes between the second supply voltage rail (VDD) and a first output node (212) and having its control node coupled to the detection node (204), wherein the switch (206) is controlled based on a voltage at the first output node (212).
摘要翻译： 本发明涉及一种光链路的光接收器，其具有耦合在检测节点（204）和第一电源电压轨（GND）之间的光电二极管（202），所述光电二极管适于接收包括脉冲的光时钟信号; 耦合在检测节点（204）和第二电源电压轨（VDD）之间的开关（206）; 以及第一晶体管（211），其第二电源电压轨（VDD）和第一输出节点（212）之间的主要导电节点耦合，并且其控制节点耦合到检测节点（204），其中开关（206） 基于第一输出节点（212）处的电压来控制。
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7.发明公开Method and apparatus for coordinating memory operations among diversely-located memory components 有权用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2849075A1
公开(公告)日：2015-03-18
申请号：EP14196752.1
申请日：2002-04-23
申请人： Rambus Inc.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
摘要翻译： 一种用于多样-位于存储器组件之间进行协调的存储器操作的方法和装置进行说明。 在与本发明的实施方式雅舞蹈，波浪流水线被实现为解决耦合到存储器元件的多个汇流。 存储器组件的多元性是被配置gemäß到坐标与地址总线传播延迟和数据总线传播延迟。 哪个复制合成信号的传播延迟与地址和/或控制信号相关联的定时信号用于协调存储器操作。
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8.发明公开Method and apparatus for coordinating memory operations among diversely-located memory components 有权用于协调不同位置的存储器组件之间的存储器操作的方法和装置
公开(公告)号：EP2278474A1
公开(公告)日：2011-01-26
申请号：EP10178677.0
申请日：2002-04-23
申请人： Rambus Inc.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
摘要翻译： 描述了用于协调不同定位的存储器组件之间的存储器操作的方法和装置。 根据本发明的实施例，对于耦合到多个存储器组件的地址总线实施波浪流水线。 根据与地址总线传播延迟和数据总线传播延迟相关的坐标来配置多个存储器组件。 与复制这些信号的传播延迟的地址和/或控制信号相关的定时信号被用于协调存储器操作。
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9.发明公开
公开(公告)号：EP2275943A1
公开(公告)日：2011-01-19
申请号：EP10179117.6
申请日：2002-04-23
申请人： Rambus Inc.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
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