公开(公告)号：EP4390748A1

公开(公告)日：2024-06-26

申请号：EP23217567.9

申请日：2023-12-18

申请人： MediaTek Inc.

发明人： CHIN, Pang-Yen ,  LIN, Yu-Sian ,  ZENG, Ri-Cheng ,  CHENG, Chi-Shun ,  TSENG, Wei-Hsin ,  CHEN, Kuan-Ta ,  HU, Chia-Hsin

IPC分类号： G06F30/38 ,  G06F30/39 ,  G06F111/20 ,  G06F117/12 ,  G06F119/20

CPC分类号： G06F30/39 ,  G06F2111/2020200101 ,  G06F2117/1220200101 ,  G06F2119/2020200101 ,  G06F30/398 ,  G06F30/38

摘要： A method for designing an integrated circuit layout includes: generating an analog standard cell library and designing the integrated circuit layout by using at least the analog standard cell library, where the step of generating the analog standard cell library includes creating a target analog standard cell that is included in the analog standard cell library and does not violate layout rules of digital standard cells. Another method for designing an integrated circuit layout includes: generating a mixed-signal standard cell library and designing the integrated circuit layout by using at least the mixed-signal standard cell library, where the step of generating the mixed-signal standard cell library includes creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells.

公开(公告)号：EP4437448A1

公开(公告)日：2024-10-02

申请号：EP22839016.7

申请日：2022-11-11

申请人： Achronix Semiconductor Corporation

发明人： RIEPE, Michael ,  CHOUNDHARY, Kamal ,  SINGH, Amit ,  JAWALE, Shirish ,  KOEHLER, Karl ,  LONGCROFT, Simon ,  SENST, Scott ,  HILBERT, Clark ,  ORTHNER, Kent

IPC分类号： G06F30/347 ,  G06F30/343 ,  G06F119/20

CPC分类号： G06F30/343 ,  G06F30/347 ,  G06F2119/2020200101

公开(公告)号：EP4427161A1

公开(公告)日：2024-09-11

申请号：EP22840392.9

申请日：2022-11-18

申请人： Siemens Industry Software Inc.

发明人： LINDER, James D. ,  GAIKWAD, Janardan

IPC分类号： G06F30/10 ,  G06F30/17 ,  G06Q10/0633 ,  G05B19/4097 ,  G06F111/16

CPC分类号： G06F30/10 ,  G06F2111/1620200101 ,  G06Q10/0633 ,  G06F2111/0220200101 ,  G06F2119/2020200101

公开(公告)号：EP4404097A1

公开(公告)日：2024-07-24

申请号：EP24152431.3

申请日：2024-01-17

申请人： Arteris, Inc.

发明人： CHARIF, Amir ,  VAN RUYMBEKE, Xavier

IPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/394 ,  G06F119/20 ,  G06F115/02

CPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/394 ,  G06F2115/0220200101 ,  G06F2119/2020200101

摘要： System and methods are disclosed for generation and synthesis of networks, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.

公开(公告)号：EP4158499B1

公开(公告)日：2024-04-24

申请号：EP21746354.6

申请日：2021-07-07

IPC分类号： G06F16/36 ,  G06N5/02 ,  G06F16/9032 ,  G06F30/20 ,  G06Q10/06 ,  G06F16/951

CPC分类号： G06F16/367 ,  G06F16/90332 ,  G06F16/951 ,  G06N5/022 ,  G06F30/13 ,  G06F2119/2020200101 ,  G06F2111/2020200101