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377 条记录 (耗时 0.093 秒)

    Memory access collision avoidance scheme
    91.
    发明公开
    Memory access collision avoidance scheme 有权
    Verfahren und Vorrichtung zur Vermeidung von Speicherzugriffskonflikten

    公开(公告)号：EP1406265A1

    公开(公告)日：2004-04-07

    申请号：EP02368107.5

    申请日：2002-10-02

    申请人： Dialog Semiconductor GmbH

    发明人： Engelhardt, Markus

    IPC分类号： G11C7/22 ,  G11C8/16

    CPC分类号： G11C7/22 ,  G11C7/1075

    摘要： A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) (120) are described. Serial write access by means of a serial interface (110) and read access with a read strobe from an independent read device (130) are generated asynchronously. Prerequisites for the implementation are:
    firstly, use of a serial interface (110) providing a serial clock signal;
    secondly, write access to SPRAM (120) has to occur at the end of serial transmission:
    thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.

    摘要翻译： 该方法包括利用来自串行接口（110）的时钟信号和来自读取装置的原始读取选通信号，以对单个端口RAM（120）的异步读取访问。 生成用于对RAM的异步读取访问的单个修改的读取选通信号，以便每当串行写入和异步读取访问发生时，避免同时访问读取和写入操作。 还包括一个独立的声明，用于在单端口RAM的读写操作期间避免访问冲突。

    Block write power reduction
    94.
    发明公开
    Block write power reduction 失效
    块写在省电

    公开(公告)号：EP0810607A3

    公开(公告)日：1999-06-09

    申请号：EP97107334.1

    申请日：1997-05-03

    申请人： Hyundai Electronics America, Inc.

    发明人： Pinkham, Ray ,  Yeo, Cheow F.

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1075

    摘要： A video memory device has a normal write mode and a block write mode, and includes a global write driver driving global input/output (I/O) lines, and a number of local write drivers, each driving local I/O lines coupled to a number of memory cells. Control circuitry is coupled to the global write driver and to the local write drivers, and is adapted to generate block write control signals and normal write control signals. The block write control signals cause the write data path to freeze during a block write cycle, thereby conserving power during block writes.

    MEMORY
    96.
    发明公开
    MEMORY 失效
    斯派克

    公开(公告)号：EP0872847A4

    公开(公告)日：1999-01-13

    申请号：EP97909696

    申请日：1997-10-30

    申请人： OKI ELECTRIC IND CO LTD

    发明人： TAKASUGI ATUSHI

    IPC分类号： G11C11/401 ,  G06T1/60 ,  G11C7/10 ,  G11C11/406 ,  H04N5/907 ,  G11C11/407

    CPC分类号： G11C7/1075 ,  G11C11/406

    摘要： A memory wherein the refresh control is improved by integrating a multiport DRAM and a general-purpose DRAM into one chip and making the X addresses of the two kinds of DRAMs consecutive and making the Y addresses common and making the control terminals common, excellence in cost performance being attained by mounting a DRAM used as a temporary buffer mixedly thereby reducing the board area, without marring the strong point of a conventional multiport DRAM.

    摘要翻译： 其中通过将多端口DRAM和通用DRAM集成到一个芯片中并且使得两种DRAM的X地址连续并使Y地址公用并使控制终端通用来改进刷新控制的存储器，成本优异 通过将混合使用的DRAM用作临时缓冲器来实现性能，从而减小了电路板面积，而不损害传统多端口DRAM的优点。

    HIGH PERFORMANCE UNIVERSAL MULTI-PORT INTERNALLY CACHED DYNAMIC RANDOM ACCESS MEMORY SYSTEM, ARCHITECTURE AND METHOD
    99.
    发明公开
    HIGH PERFORMANCE UNIVERSAL MULTI-PORT INTERNALLY CACHED DYNAMIC RANDOM ACCESS MEMORY SYSTEM, ARCHITECTURE AND METHOD 失效
    系统架构和方法具有高性能与内部缓存通用多端口动态随机存取存储器

    公开(公告)号：EP0870303A1

    公开(公告)日：1998-10-14

    申请号：EP96925929.0

    申请日：1996-08-12

    申请人： Chatter, Mukesh

    发明人： Chatter, Mukesh

    IPC分类号： G06F12 ,  G06F13 ,  G09G5 ,  G11C7 ,  G11C11

    CPC分类号： G11C7/1075 ,  G06F12/0893 ,  G06F13/16

    摘要： A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called 'AMPIC DRAM', and consequentially a unique system architecture which eliminates current serious system bandwidth limitations. It also provides a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach. The chip also interconnects significantly higher numbers of resources with substantially enhanced performance and at notably lower cost. A system configuration based on this novel architecte can work equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

    MULTI-BIT BLOCK WRITE IN A RANDOM ACCESS MEMORY
    100.
    发明公开
    MULTI-BIT BLOCK WRITE IN A RANDOM ACCESS MEMORY 失效
    多位块传输写在一个动态随机存取存储器

    公开(公告)号：EP0826216A2

    公开(公告)日：1998-03-04

    申请号：EP96913990.0

    申请日：1996-05-10

    申请人： MICRON TECHNOLOGY, INC.

    发明人： MCLAURY, Loren, L.

    IPC分类号： G11C11 ,  G11C7

    CPC分类号： G11C7/1078 ,  G11C7/1033 ,  G11C7/1075

    摘要： An integrated circuit memory is described which has a multi-bit write register. Each plane of the multi-bit write register has a plurality of bits, or columns. The multi-bit write register allows each memory cell in a block of selected memory cells of the integrated circuit memory to be block written to a different logic state. The write register can be a color register in a multi-port memory device, or a single port device. Several methods of loading the write register are also described. These methods include loading the write register one column at a time or one plane at a time. The columns or planes can be loaded in either a pre-determined pattern, or selectively loaded.