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    MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME
    2.
    发明公开
    MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：EP4456069A1

    公开(公告)日：2024-10-30

    申请号：EP23208292.5

    申请日：2023-11-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： YANG, Yunseok ,  JEONG, Yunkyeong ,  SHIN, Jaewoo ,  AN, Minhwan ,  CHUNG, Jin Suk

    IPC分类号： G11C5/04 ,  G11C7/10 ,  G11C11/4093

    摘要： A memory device (110) includes a first physical interface (111), a second physical interface (112), a first memory core (113), a second memory core (114), and a setting circuit. The first memory core (113) is assigned to the first physical interface (111) and includes a plurality of first stacked memory dies (431 to 438) and connected via a through electrode. The second memory core (114) is assigned to the second physical interface (112) and includes a plurality of second stacked memory dies (441 to 448) connected via a through electrode. The setting circuit sets at least one physical interface to be used for connection with an external device (120) of the memory device (110) among the first physical interface (111) and the second physical interface (112).

    CONFIGURABLE DATA PATH FOR MEMORY MODULES
    3.
    发明公开
    CONFIGURABLE DATA PATH FOR MEMORY MODULES 审中-公开

    公开(公告)号：EP4407464A3

    公开(公告)日：2024-10-30

    申请号：EP24181782.4

    申请日：2019-12-16

    申请人： Micron Technology, Inc.

    发明人： KINSLEY, Thomas, H.

    IPC分类号： G11C7/10 ,  G11C29/42 ,  G06F11/10

    摘要： Systems and methods are described to enable a memory device integrated in a memory module or system to disable one or more data bits, nibbles or bytes of the memory device., The memory device can be further configured to disable error or redundancy checking associated with the disabled data bits, nibbles or bytes, to mask errors associated with the disabled data bits, nibbles or bytes, and/or to suppress the refresh of portions of a memory array associated with the disabled data bits, nibbles or bytes.

    MEMORY DEVICE WITH INTERPLANE PAD PART
    6.
    发明公开
    MEMORY DEVICE WITH INTERPLANE PAD PART 审中-公开

    公开(公告)号：EP4447049A1

    公开(公告)日：2024-10-16

    申请号：EP24157343.5

    申请日：2024-02-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： LEE, Myunghun ,  SHIN, Homoon

    IPC分类号： G11C5/02 ,  G11C7/18 ,  H10B41/20 ,  H10B41/40

    摘要： A memory device may include a first structure (ST1) and a second structure (ST2) bonded to the first structure (ST1). The first structure (ST1) may have a plurality of planes (PL1-PL6) and a pad part (PDP; PDP1, PDP2) between two planes adjacent to each other among the plurality of planes (PL1-PL6). Each of the plurality of planes (PL1-PL6) may include a memory cell. The second structure (ST2) may include a peripheral circuit. The plurality of planes (PL1-PL6) may be minimum units in which operations are independently performed and may be in an n x m array (n and m being integers of 2 or larger). The pad part (PDP; PDP1, PDP2) may be between the rows and/or between the columns of the n x m array.