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    Semiconductor device with high off-breakdown-voltage and low on-resistance and method of manufacturing the same
    92.
    发明公开
    Semiconductor device with high off-breakdown-voltage and low on-resistance and method of manufacturing the same 失效
    具有高开关击穿电压和低Anschaltwiderstand和它们的制备方法的半导体器件。

    公开(公告)号：EP0519632A2

    公开(公告)日：1992-12-23

    申请号：EP92305263.3

    申请日：1992-06-09

    申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

    发明人： Terashima, Tomohide, c/o Mitsubishi Denki K.K.

    IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66734 ,  H01L21/187 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7813 ,  Y10S148/05 ,  Y10S438/977

    摘要： A semiconductor device includes an N⁻ type semiconductor layer (2). The N⁻ type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N⁺ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N⁺ type semiconductor substrate (1). With higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10).
    Hence, even when process patterns are refined, electrode-to-electrode insulation remains undegraded in the semiconductor device, attaining low on-resistance and high off-breakdown voltage.

    摘要翻译： 一种半导体器件，包括：在N个< - >型半导体层（2）。 所述N个< - >型半导体层（2）包括三角形极沟槽（10）上的顶点部分其包含栅电极（5）。 该沟槽（10）穿过所述半导体层（2）和P型阱区域（3）和伸入到在N个<+>型源极区域（4）。 源电极（7）被布置为从半导体层（2）通过在氧化物电影（9）和与所述阱区域（3）和（4）在源极区域接触绝缘。 漏电极（8）通过在N个连接到半导体层（2）<+>类型的半导体衬底（1）。 与在栅极电极（5）比在源电极（7），阱区域（3）被部分反相到沟槽（10）附近的N型高电位。 因此，该半导体器件被接通，由于创建相关联的导电类型反型沟道。 大多数电流流动的允许进入通过沟槽（10）附近的通道中流动的半导体层（2）。 因此，即使当处理模式被精制而成，电极 - 电极绝缘保持在半导体器件未降解，获得低导通电阻和高截止击穿电压。

    A Lateral transistor and method of making same
    93.
    发明公开
    A Lateral transistor and method of making same 失效
    一种横向晶体管及其制造方法

    公开(公告)号：EP0392954A3

    公开(公告)日：1992-08-12

    申请号：EP90480025.7

    申请日：1990-02-20

    申请人： International Business Machines Corporation

    发明人： Desilets, Brian Henry ,  Hsieh, Chang-Ming ,  Hsu, Louis Lu-Chen

    IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/73

    CPC分类号： H01L29/6625 ,  H01L21/763 ,  H01L29/41708 ,  H01L29/735 ,  Y10S148/05

    摘要： A method of fabricating a lateral transistor (110) is provided, including the steps of: providing a body of semiconductor material including a device region (30) of a first conductivity type (N⁺); patterning the surface of the device region to define a first transistor region (44); filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of said first transistor region; removing portions of the insulating material so as to define a pair of trenches (22) generally bounding opposite sides of the first tran­sistor region; filling the pair of trenches with doped conductive material (26) of opposite conductivity type to the first transistor region; and annealing the semiconduc­tor body whereby to form second and third transistor regions (96,98) of opposite conductivity type to the first transistor region (44) in the opposing sides of the first transistor region completing the process to provide con­tact electrodes (102, 104, 106).

    Method of manufacturing a semiconductor substrate having a dielectric isolation structure
    95.
    发明公开
    Method of manufacturing a semiconductor substrate having a dielectric isolation structure 失效
    一种用于制造具有介电隔离结构的半导体衬底的过程。

    公开(公告)号：EP0488230A2

    公开(公告)日：1992-06-03

    申请号：EP91120294.3

    申请日：1991-11-27

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Hoshi, Tadahide

    IPC分类号： H01L21/76

    CPC分类号： H01L21/3212 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/763 ,  Y10S148/05

    摘要： In accordance with this invention, in manufacturing a semiconductor substrate having a dielectric isolation structure, an approach is employed to form a dielectric film at a semiconductor layer (32) formed by epitaxial growth and grooves for carrying out dielectric isolation to deposit filler (36) thereon thereafter to polish the deposited filler by using the polishing condition where the polishing rate ratio of the filler to the dielectric film is one fifth or less. Thus, an active semiconductor layer where elements are to be formed can be provided with good productivity under the state where the flatness thereof is good and the layer thickness is uniformly and precisely controlled.

    摘要翻译： 与本发明雅舞蹈，在制造具有电介质隔离结构的半导体衬底，在方法被用来形成电介质膜在半导体层（32），通过外延生长和用于进行介质隔离来沉积填充材料的槽（36）而形成 其上后，使用抛光条件，其中填料与电介质的研磨速度比薄膜是五分之一或更少以抛光该沉积填料。 因此，当元件要形成可以的状态下被提供有良好的生产率，其中它们的平坦性良好，层厚度均匀地和精确地控制有源半导体层上。

    PROCESS FOR TRENCH OXIDE ISOLATION OF INTEGRATED DEVICES
    99.
    发明授权
    PROCESS FOR TRENCH OXIDE ISOLATION OF INTEGRATED DEVICES 失效
    一体化装置的氧化铁分离过程

    公开(公告)号：EP0245493B1

    公开(公告)日：1991-06-19

    申请号：EP87900371.3

    申请日：1986-11-10

    申请人： NCR CORPORATION

    发明人： ELLSWORTH, Daniel, Lloyd ,  CRAVENS, Scott, Harris ,  MOLL, Maurice, Michael

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/31604 ,  Y10S148/05 ,  Y10S148/111

    摘要： In a process for forming dielectrically filled planarized trenches (4; 138, 139) of arbitrary width in a semiconductor substrate (100), a first mask (A) defines active regions (112-114) and subdivides the trench isolation regions into a succession of the trench and plateau regions, where the widths of the trench and plateau regions fall within a dimensional range constrained by the photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask (A) in place, the substrate (100) is anisotropically etched to form first trenches (117, 118, 119, 121). A conformal deposition of dielectric (124) follows, to form substantially void free trench dielectric, following which the surface is planarized. Next, a second mask (B), defined to be slightly larger than the active regions (112-114), is formed over the substrate (100). A selective etch is then applied to remove the plateau regions (122, 123) and thereby form new trenches approximating in depth the first trenches. A second conformal deposition of dielectric (137) follows, whereafter the surface is again planarized. The substrate surface is now planar and divided into active regions (1-3; 112-114) which are separated by oxide filled, arbitrary width trenches (4; 138, 139).

    Verfahren zur Erzeugung eines Streifenwellenleiters in einer epitaktischen Hetero-Schichtstruktur
    100.
    发明公开
    Verfahren zur Erzeugung eines Streifenwellenleiters in einer epitaktischen Hetero-Schichtstruktur 失效
    在外延层间结构中生产条状波导的方法

    公开(公告)号：EP0262440A3

    公开(公告)日：1991-02-27

    申请号：EP87112828.6

    申请日：1987-09-02

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Heinen, Jochen, Dr.

    IPC分类号： G02B6/10 ,  H01S3/19 ,  H01L21/208

    CPC分类号： G02B6/136 ,  H01S5/227 ,  H01S5/2275 ,  Y10S148/029 ,  Y10S148/05 ,  Y10S148/065 ,  Y10S148/066 ,  Y10S148/072 ,  Y10S148/108 ,  Y10S438/955

    摘要： Verfahren zur Erzeugung eines Streifenwellenleiters (2) mit BH-Schicht­struktur, wobei aus der Schichtstruktur ein erhabener Streifen (1) herausgeätzt und dieser Streifen (1) mittels einer Abtrag­schmelze seitlich angelöst wird. Bei bekannten derartigen Ver­fahren werden die seitlichen Begrenzungsflächen (21, 22) des Streifens (1) einer Atmosphäre und/oder Chemikalien ausgesetzt. Dadurch haben diese Flächen eine verminderte Qualität, die Ursache für Alterungsmechanismen sind, die ein solcher Streifen­wellenleiter (2) zeigt. Zur Erzielung seitlicher Begrenzungsflächen hoher Perfektion wird so vorgegangen, daß die seitlichen Begrenzungs­flächen (21, 22) der wellenleitenden Schicht (2) des Streifen­wellenleiters von einem von der Abtragschmelze gelösten Teil (5) dieser Schicht (2) abgedeckt belassen werden, und daß dieser Teil (5) mit als Wachstumsschmelze zur Erzeugung einer seitlich an die wellenleitende Schicht (2) angrenzenden Epitaxieschicht (6) verwendet wird.

    摘要翻译： 一种用于在由层组成的掩埋异质结构中产生条状激光的方法，其中凸起的条被蚀刻出层结构，并且带被侵蚀熔融物横向蚀刻。 激光活性层的侧边缘通过将其被被侵蚀熔体溶出的一部分层所覆盖而被保护。 这样保留的沉积物被用来引发从激光有源层横向延伸的外延层的产生。