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142 条记录 (耗时 0.019 秒)

    On-chip PLL phase and jitter self-test circuit
    93.
    发明授权
    On-chip PLL phase and jitter self-test circuit 失效
    集成电路与锁相环和内建自测试相位和相位抖动

    公开(公告)号：EP0889411B1

    公开(公告)日：2003-06-04

    申请号：EP98305134.3

    申请日：1998-06-29

    申请人： Sun Microsystems, Inc.

    发明人： Smith, Larry D. ,  ABT, Norman E.

    IPC分类号： G06F11/24 ,  G01R25/00

    CPC分类号： G01R31/31709 ,  G01R29/26 ,  G01R31/30 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087

    摘要： An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1 DELTA t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) DELTA t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized. The digitized output signal identifies the lowest duty cycle two-input logic element, and thus phase shift. The relative breadth of the integrated capacitor voltage profile provides a measure of average maximum jitter.

    CMOS integrated circuit failure diagnosis apparatus and diagnostic method
    95.
    发明授权
    CMOS integrated circuit failure diagnosis apparatus and diagnostic method 失效
    用于CMOS集成电路和诊断程序的诊断装置

    公开(公告)号：EP0785513B1

    公开(公告)日：2002-05-02

    申请号：EP97100416.3

    申请日：1997-01-13

    申请人： NEC CORPORATION

    发明人： Sakaguchi, Kazuhiro

    IPC分类号： G06F11/24 ,  G06F11/26 ,  G01R31/30

    CPC分类号： G01R31/3008 ,  G01R31/30 ,  G01R31/3004 ,  G01R31/318342 ,  G06F11/22 ,  G06F11/261

    摘要： A failure diagnosis apparatus is provided which predicts failure locations in a CMOS integrated circuit in which an Iddq has been discovered, this apparatus having a test pattern storage unit 1 for storing test patterns used to perform a functional test of the CMOS integrated circuit, an LSI tester 3 which performs a functional test and an Iddq test on the CMOS integrated circuit based on the test patterns, a test results storage unit 6 to store test results, a circuit data storage unit 2 to store various information with regard to the device under test, a logic simulator 5 for receiving the above-noted test patterns and circuit data and performing a logic simulation of the internal operation of the circuit, a simulation results storage unit 7, and a failure location judgment unit 8 for outputting the diagnosis results based on test results and simulation results. This diagnosis apparatus predicts short circuit failures between signal lines and between a signal line and either a power supply line or a ground line, based, on the results of a simulation of internal circuit signal values at a point in time at which a test pattern is applied for which an abnormality is not detected in an Iddq test.

    Ciruit and method to externally adjust internal circuit timing
    97.
    发明公开
    Ciruit and method to externally adjust internal circuit timing 审中-公开
    Vorrichtung und Verfahren zur externen Einstellung einer internen Zeitgeberschaltung

    公开(公告)号：EP0903755A2

    公开(公告)日：1999-03-24

    申请号：EP98307137.4

    申请日：1998-09-04

    申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

    发明人： Wong, Hing ,  Kirihata, Toshiaki ,  Krsnik, Bozidar

    IPC分类号： G11C29/00 ,  G06F11/24

    CPC分类号： G11C7/22 ,  G01R31/3016

    摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

    摘要翻译： 一种使用测试模式来使用集成电路中的外部控制来控制内部信号的定时的电路和方法。 测试模式被设计为使得内部信号的定时来自外部控制，其可由测试仪任意控制。 外部信号可以应用于现有的针脚进行芯片控制，只要测试模式与集成电路的运行没有冲突。

    Module-configurable, full-chip power profiler
    98.
    发明公开
    Module-configurable, full-chip power profiler 失效
    模块化配件，auf einen ganzen芯片anwendbarer Leistungsprofilgenerator

    公开(公告)号：EP0875833A1

    公开(公告)日：1998-11-04

    申请号：EP98303367.1

    申请日：1998-04-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Hurd, Linda

    IPC分类号： G06F11/24 ,  G06F17/50

    CPC分类号： G06F9/3885 ,  G01R21/133 ,  G01R31/3004 ,  G06F1/26 ,  G06F9/3891 ,  G06F17/5022 ,  G06F2217/78

    摘要： A method for determining the power consumption, resulting from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules. The method involves the steps of, first, providing a set of average current values for each of the modules, for a predetermined plurality of sets of conditions (fig.7) based on predetermined sets of signal line states associated with the module, for each instruction in the instruction set of the processor module, the sets of conditions being selected for dominant power consumption effect on the module. For each module, for each instruction in a block of code to be executed on the processor module, a set of signal line states is generated, associated with the module, for each processor cycle, in sequence. The generated set of signal line states are then tested for the set of conditions(128). One of the average current values is assigned for each condition so tested that is met. Finally, the running total of the average current values so met is accumulated for each such processor cycle(180). The average current values can be translated for different frequencies and supply voltages(112). Also, average current can be converted to average power consumption(118).

    摘要翻译： 一种用于确定包括处理器模块和一个或多个其它电路模块的集成电路的代码块执行所产生的功耗的方法。 该方法包括以下步骤：首先，基于与模块相关联的预定的信号线状态组，为每个模块提供一组平均电流值，用于预定的多组条件（图7），对于每个模块 指令在处理器模块的指令集中，所选择的条件集合用于主要功耗对模块的影响。 对于每个模块，对于要在处理器模块上执行的代码块中的每个指令，依次为每个处理器周期生成与模块相关联的一组信号线状态。 然后根据条件集（128）测试所生成的信号线状态集合。 为满足这样测试的每个条件分配一个平均当前值。 最后，对于每个这样的处理器周期（180）累积如此满足的平均电流值的运行总和。 平均电流值可以转换为不同的频率和电源电压（112）。 此外，平均电流可以转换为平均功耗（118）。

    Leakage current control system for low voltage CMOS circuits
    99.
    发明公开
    Leakage current control system for low voltage CMOS circuits 失效
    LeckstromregelungsystemfürNiederspannung-CMOS-Schaltungen

    公开(公告)号：EP0773448A1

    公开(公告)日：1997-05-14

    申请号：EP96630062.6

    申请日：1996-11-08

    申请人： SUN MICROSYSTEMS INC.

    发明人： Fowler, Boyd

    IPC分类号： G01R31/28 ,  G06F11/24

    CPC分类号： G01R31/3004

    摘要： A leakage current control circuit for controlling leakage current within a semiconductor region includes a current source, a biasing circuit and a test device integrated within the semiconductor region. Where the semiconductor region is P-type, such as a P-type integrated circuit substrate, the test device is an N-MOS transistor, and where the semiconductor region is N-type, such as an N-well within a P-type integrated circuit substrate, the test device is a P-MOS transistor. The MOS transistor has its gate and source terminals shorted together so that any current flowing through it will be leakage current only. The current source provides an input signal to the MOS transistor and biasing circuit. The biasing circuit compares the input signal to a reference signal to which the desired leakage current corresponds and, based upon such comparison, applies a bias signal to the semiconductor region which is also the bulk terminal for the MOS transistor. Based upon such applied bias signal, the leakage current flowing through the MOS transistor can be selected in accordance with the reference signal applied to the biasing circuit.

    摘要翻译： 用于控制半导体区域内的漏电流的漏电流控制电路包括集成在半导体区域内的电流源，偏置电路和测试装置。 如果半导体区域是P型，例如P型集成电路衬底，则测试装置是N-MOS晶体管，并且其中半导体区域是N型，诸如P型内的N阱 集成电路基板，测试装置是P-MOS晶体管。 MOS晶体管的栅极和源极端子短路在一起，所以流过它的任何电流只会是漏电流。 电流源向MOS晶体管和偏置电路提供输入信号。 偏置电路将输入信号与期望的泄漏电流对应的参考信号进行比较，并且基于这种比较，将偏置信号施加到也是用于MOS晶体管的体积端子的半导体区域。 基于这种施加的偏置信号，可以根据施加到偏置电路的参考信号来选择流过MOS晶体管的漏电流。

    Structural and performance scan test
    100.
    发明公开
    Structural and performance scan test 失效
    结构和性能扫描测试

    公开(公告)号：EP0702241A2

    公开(公告)日：1996-03-20

    申请号：EP95305861.7

    申请日：1995-08-22

    申请人： SGS-THOMSON MICROELECTRONICS LTD.

    发明人： Warren, Robert

    IPC分类号： G01R31/3173 ,  G01R31/3185 ,  G06F11/24 ,  G06F11/267 ,  H03K3/037

    CPC分类号： G06F11/2236 ,  G01R31/31858 ,  H03K3/0375

    摘要： A method of testing the performance of a combinational logic circuit is described. In contrast to a structural test, a performance test allows the performance of a combinational logic circuit to be tested by determining the accuracy of a set of outputs resulting from a change in input bits to the combinational logic circuit. Thus, it is possible to monitor more closely the timing aspects of a combinational logic circuit.

    摘要翻译： 描述了测试组合逻辑电路的性能的方法。 与结构测试相比，性能测试允许通过确定组合逻辑电路的输入位变化导致的一组输出的准确度来测试组合逻辑电路的性能。 因此，可以更密切地监视组合逻辑电路的时序方面。