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55 条记录 (耗时 0.026 秒)

    STORAGE DEVICE
    13.
    发明公开
    STORAGE DEVICE 审中-公开

    公开(公告)号：EP3486910A1

    公开(公告)日：2019-05-22

    申请号：EP16908828.3

    申请日：2016-07-13

    申请人： Toshiba Memory Corporation

    发明人： SUGAHARA, Akio ,  NAGAI, Yuji

    IPC分类号： G11C16/06 ,  G06F12/06

    摘要： A memory device includes a memory cell array configured to store data, a control circuit configured to control the memory cell array in response to a command; and a receiver configured to be placed in an active state based on a first signal, a second signal, or an operation result of an address and the command, and be enabled to receive a command or data.

    AUTHENTICATOR, AUTHENTICATEE AND AUTHENTICATION METHOD
    14.
    发明公开
    AUTHENTICATOR, AUTHENTICATEE AND AUTHENTICATION METHOD 审中-公开

    公开(公告)号：EP3454236A1

    公开(公告)日：2019-03-13

    申请号：EP18203058.5

    申请日：2012-03-19

    申请人： TOSHIBA MEMORY CORPORATION

    发明人： Kato, Taku ,  Matsushita, Tatsuyuki ,  Nagai, Yuji ,  Zhao, Fangming

    IPC分类号： G06F21/00 ,  G06F21/44 ,  G06F21/73 ,  G06F21/42

    摘要： According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey).

    SEMICONDUCTOR STORAGE DEVICE
    15.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：EP3404697A1

    公开(公告)日：2018-11-21

    申请号：EP16884905.7

    申请日：2016-01-13

    申请人： Toshiba Memory Corporation

    发明人： FUTATSUYAMA, Takuya

    IPC分类号： H01L21/00

    CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C5/063 ,  G11C7/12 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4085 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

    摘要： A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region (CEL), a second region (WLHU) adjacent to the first region (CEL) in the first direction (Y-direction), and a third region (CNCT) configured to connect the first region (CEL) and the second region (WLHU) . The memory cell array further includes : a first insulating layer (730) buried in a first trench (DY) between the first region (CEL) and the second region (WLHU) and in contact with the third region (CNCT) ; a first contact plug (CP12) provided in the first insulating layer (730) and electrically connected to the row decoder; and a first interconnect (IC1) configured to connect a selection gate line (SGD) and the first contact plug (CP12) .

    CARD AND HOST DEVICE
    17.
    发明授权
    CARD AND HOST DEVICE 有权
    卡和主机设备

    公开(公告)号：EP1816590B1

    公开(公告)日：2018-03-07

    申请号：EP05809616.5

    申请日：2005-11-25

    申请人： TOSHIBA MEMORY CORPORATION

    发明人： FUJIMOTO, Akihisa

    IPC分类号： G06K17/00 ,  G06K19/07 ,  G06F1/26

    CPC分类号： G06F3/0679 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0659 ,  G06F2003/0697 ,  G06F2206/1014 ,  G11C5/143 ,  H04L1/0061 ,  H04L2001/0094

    摘要： A host device (2) is configured to read and write information from and into a card (1) and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command (CMDA) to the card. The voltage identification command includes a voltage range identification section (VOLS), an error detection section (ED), and a check pattern section (CPS). The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.

    Semiconductor memory device
    18.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：EP2372550B1

    公开(公告)日：2018-01-17

    申请号：EP11155975.3

    申请日：2011-02-25

    申请人： Toshiba Memory Corporation

    发明人： Kanno, Shinichi

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1068 ,  G06F11/1012 ,  G06F11/1072 ,  G06F11/1076 ,  G11C16/10 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/2906

    摘要： A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.