摘要:
Dispositif servant à monter rotatif un navire flottant (1) sur une bouée submergée de chargement et de déchargement (2) ancrée au fond de la mer. Ladite bouée (2) est conçue pour s'introduire et se verrouiller de façon détachable dans un espace de réception submergé et ouvert vers le bas (3) situé dans le navire (1). La bouée (2), en fonctionnement, est accouplée à au moins une conduite de transfert (4) et constitue un accouplement de transfert entre ladite conduite (4) et un système de tube (10) situé sur le navire. La bouée (2) comprend un élément extérieur (15) conçu pour se fixer rigidement dans l'espace de réception (3), ainsi qu'un élément intérieur central (16) monté rotatif dans ledit élément extérieur (15), de façon que le navire (1) puisse tourner autour de l'élément central (16), quand la bouée (2) est verrouillée dans l'espace de réception (3). De plus, l'extrémité supérieure de l'élément central (16) est accouplée au système de tube (10) du navire par l'intermédiaire d'un moyen pivotant (31) et par l'intermédiaire d'au moins un moyen d'articulation souple (33, 34).
摘要:
Mécanisme de verrouillage à enclenchement et à déclenchement servant à fixer une bouée de chargement et de déchargement (2) à un navire (1). Ladite bouée (2) est conçue pour s'introduire dans un espace de réception (3) submergé, ouvert vers le bas et situé dans le navire (1), ainsi que pour se fixer de façon détachable dans ledit espace. Le mécanisme comprend des éléments de verrouillage (40) à actionnement hydraulique et montés autour d'axes horizontaux (41) situés sur les côtés de l'espace de réception (3), de façon à pivoter entre les positions d'enclenchement et de déclenchement du verrouillage. Ladite bouée (2) possède un collier périphérique (20) pourvu d'un bord de butée (21) tourné vers le bas, de façon à s'accoupler avec les éléments de verrouillage (40) en position d'enclenchement du verrouillage.
摘要:
Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit (229) moves the buffer (21) to slow response mode in response to the high impedance signal (GTSB). When the slew race control circuit (229) receives a signal ending the high impedance state of the buffer (21), it applies a delay to this signal, and after the delay time allows the buffer (21) to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
摘要:
Dans cette invention on rend axialement compacte une unité de pompe contrarotative ou une unité de compresseur en faisant s'écouler le fluide dans des parties concentriques et annulaires de passage pour l'écoulement entre lesquelles on inverse le sens de l'écoulement. L'unité peut comprendre des gaines (31, 32, 35) contrarotatives concentriques pourvues de palettes ou de lames agitatrices qui définissent entre elles les parties de passage pour l'écoulement, ou bien des ensembles d'ailes agitatrices contrarotatives axialement adjacents comportants chacun des anneaux concentriques entre lesquels sont intercalées des palettes agitatrices. L'inversion du sens de l'écoulement peut être effectuée par des parties de carter fixes coopérant avec les gaines ou les anneaux, ou bien par des parois annulaires (34, 62) reliant les gaines (31, 32, 35) ou les anneaux alternés.
摘要:
A pipe system comprises a plurality of pipe members (2), mechanical connections at the end regions of the pipe members whereby the pipe members can be connected together into end-to-end relationship to provide at least one fluid flow path along them, and electrical conductors (10; 110) carried by the pipe members, the electrical conductors having contract areas (19) exposed at the end regions of the pipe members so that electrical connection between the conductors of adjacent pipe members can be effected by bridging members (25) spanning the end regions of the pipe members.
摘要:
A reference circuit for supplying current to high speed logic elements in an integrated circuit supplies less current when circuit temperature decreases while a supply voltage remains constant. The reference circuit supplies less current when the supply voltage increases while circuit temperature remains constant. A resistance with a temperature coefficient, in some embodiments a negative temperature coefficient, is used to decrease current flow in a first leg of an output mirror when temperature decreases. A feedback circuit is used to decrease current flow in the first leg of the output current mirror when the feedback circuit senses an increase in supply voltage by sensing a voltage change on a common control node of the output current mirror. The reference circuit sees many applications including supplying current to logic gates, input/output buffers, and sense amplifiers.
摘要:
A cutting or bending machine is described with a combined clutch and brake mechanism (1). Conventionally, combined clutch and brake mechanisms are desirable as they are more compact and cheaper than separate units. However, considerable heat is generated which limits the productivity of a machine with a combined mechanism. The present invention provides cooling means by way of impeller means (41) and a guide duct (45) directing the air flow uniformly through the entire volume of the combined clutch and brake mechanism (1), preferably to the outer peripheral edges of the mechanism. Thus generated heat is dissipated continuously and the machine can be operated more productively. The impeller fan and the guide duct may direct the air flow axially or radially.
摘要:
A reference circuit for supplying current to high speed logic elements in an integrated circuit supplies less current when circuit temperature decreases while a supply voltage remains constant. The reference circuit supplies less current when the supply voltage increases while circuit temperature remains constant. A resistance with a temperature coefficient, in some embodiments a negative temperature coefficient, is used to decrease current flow in a first leg of an output mirror when temperature decreases. A feedback circuit is used to decrease current flow in the first leg of the output current mirror when the feedback circuit senses an increase in supply voltage by sensing a voltage change on a common control node of the output current mirror. The reference circuit sees many applications including supplying current to logic gates, input/output buffers, and sense amplifiers.
摘要:
In a noninverting Bi-CMOS gate, one or more passgates are utilized in the control path leading to a bipolar output transistor (Q24) which switches the output of the Bi-CMOS gate. The control gate of one of the MOS transistors (Q21) of a passgate is connected to an input signal of the Bi-CMOS gate. The control gate of the other MOS transistor (Q20) is connected to the complement of the input signal. The output of the passgate is connected to the base of the bipolar output transistor (Q24). More than one such passgate connected to an input signal and its complement can be used. If multiple passgates are used, the outputs of the passgates may be tied together. This technique, utilizing the switching of the passgates with the input signals and their complements, is employed to create a family of Bi-CMOS noninverting gates such as buffers and AND gates. The propagation delay through the noninverting Bi-CMOS gates of the present invention are roughly equal to the propagation delay of a single Bi-CMOS inverter.
摘要:
An LDD lateral DMOS transistor is provided in a lightly-doped epitaxial layer (512) of a first conductivity above a substrate (505) of the same conductivity. A highly-doped buried layer (501) of the first conductivity is provided under the LDD lateral DMOS transistor to relieve crowding of electrical equipotential distribution beneath the silicon surface. In one embodiment, a gate plate (511) is provided above the gate (509) and the gate-edge of the drift region. An optional N-well (506) provides further flexibility to shape electric fields beneath the silicon surface. The buried layer (501) can also reduce the electric field in a LDD lateral diode and improves cathode-to-anode reversed-recovery characteristics.