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    APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AND PER-TAG MEMORY ACCESS
    12.
    发明公开
    APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AND PER-TAG MEMORY ACCESS 审中-公开
    DEVICE AND METHOD FOR内存访问线程和标签同步实施

    公开(公告)号：EP2601584A1

    公开(公告)日：2013-06-12

    申请号：EP11814964.0

    申请日：2011-06-30

    申请人： Sonics, INC.

    发明人： SRINIVASAN, Krishnan ,  KHAZHAKYAN, Ruben ,  ASLANYAN, Harutyun ,  WINGARD, Drew, E. ,  CHOU, Chien-chun

    IPC分类号： G06F13/00 ,  G06F1/10

    CPC分类号： G06F9/526 ,  G06F12/0879 ,  G06F12/0882

    摘要： A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

    SCHEDULING MEMORY ACCESS BETWEEN A PLURALITY OF PROCESSORS
    15.
    发明授权
    SCHEDULING MEMORY ACCESS BETWEEN A PLURALITY OF PROCESSORS 有权
    分级存储器访问多个处理器之间

    公开(公告)号：EP1678620B1

    公开(公告)日：2011-06-22

    申请号：EP04796678.3

    申请日：2004-10-27

    申请人： Sonics, Inc.

    发明人： WEBER, Wolf-Dietrich

    IPC分类号： G06F13/00

    CPC分类号： G06Q10/06395 ,  H04L47/10 ,  H04L47/2425 ,  H04L47/70 ,  H04L47/805 ,  H04L47/821 ,  H04L47/827

    摘要： In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device initiator in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.

    SHARED STORAGE FOR MULTI-THREADED ORDERED QUEUES IN AN INTERCONNECT
    19.
    发明公开
    SHARED STORAGE FOR MULTI-THREADED ORDERED QUEUES IN AN INTERCONNECT 审中-公开
    对于由多个线程顺序排队公用存储在一个电子连接

    公开(公告)号：EP2156305A1

    公开(公告)日：2010-02-24

    申请号：EP08780731.9

    申请日：2008-05-30

    申请人： Sonics, INC. ,  Hamilton, Stephen W.

    发明人： HAMILTON, Stephen, W.

    IPC分类号： G06F13/12 ,  G06F13/38

    CPC分类号： G06F13/4027 ,  G06F9/466

    摘要： In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/ or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.