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    COMMUNICATION DEVICE, SYSTEM, AND COMMUNICATION METHOD
    13.
    发明公开
    COMMUNICATION DEVICE, SYSTEM, AND COMMUNICATION METHOD 审中-公开
    KOMMUNIKATIONSVORRICHTUNG，系统在KOMMUNIKATIONSVERFAHREN

    公开(公告)号：EP2892280A1

    公开(公告)日：2015-07-08

    申请号：EP12883842.2

    申请日：2012-08-29

    申请人： Fujitsu Limited

    发明人： YAMAUCHI, Hiromasa ,  YAMASHITA, Koichiro ,  SUZUKI, Takahisa ,  KURIHARA, Koji ,  OTOMO, Toshiya ,  TERANISHI, Yuta

    IPC分类号： H04W40/04 ,  H04W4/04 ,  H04W84/18

    CPC分类号： H04Q9/00 ,  H04L67/04 ,  H04L67/1068 ,  H04L67/12 ,  H04L67/18 ,  H04W4/023 ,  H04W4/38 ,  H04W4/70 ,  H04W84/18

    摘要： A sensor node (101-1) has no subsequent assignment-destination sensor node (101), when the execution of data processing is assigned to a sensor node (101-h) that can directly communicate with a parent device (102) (dashed-lined arrow), and the data processing is not completed by the assignment-destination sensor node (101-h). Thus, when unable to execute the data processing, the sensor node (101-1) requests a sensor node (101-m) that requires plural hops in communicating with the parent device (102) (solid lined arrow). Even when the data processing is not completed by the assignment-destination sensor node (101-m), the data processing can be completed by executing the data processing in stages by plural sensor nodes (101).

    摘要翻译： 当数据处理的执行被分配给可以与父设备（102）直接通信的传感器节点（101-h）时，传感器节点（101-1）没有后续的分配目的地传感器节点（101） 并且分配目的地传感器节点（101-h）未完成数据处理。 因此，当不能执行数据处理时，传感器节点（101-1）请求与父设备（102）进行通信中需要多个跳数的传感器节点（101-m）（实线箭头）。 即使当分配目的地传感器节点（101-m）未完成数据处理时，也可以通过多个传感器节点（101）分阶段执行数据处理来完成数据处理。

    COMMUNICATION APPARATUS
    14.
    发明公开
    COMMUNICATION APPARATUS 有权
    通信设备

    公开(公告)号：EP2876970A1

    公开(公告)日：2015-05-27

    申请号：EP12881540.4

    申请日：2012-07-23

    申请人： Fujitsu Limited

    发明人： OTOMO, Toshiya ,  YAMASHITA, Koichiro ,  SUZUKI, Takahisa ,  YAMAUCHI, Hiromasa ,  KURIHARA, Koji

    IPC分类号： H04W84/18 ,  H04W4/04

    CPC分类号： H04L47/12 ,  H04L67/12 ,  H04W4/38 ,  H04W84/18

    摘要： A communication device has: a sensor configured to output sensing data; a count signal communication part configured to count a count signal received from a control device directly or via another communication device and transmit the counted count signal and to store a value of the received count signal; and a data communication part configured to transmit the sensing data outputted by the sensor or the sensing data received from another communication device, in correspondence with the stored value of the count signal.

    摘要翻译： 通信设备具有：配置成输出感测数据的传感器; 计数信号通信部分，配置为对从控制装置直接或经由另一通信装置接收的计数信号进行计数，并发送计数的计数信号并存储所接收的计数信号的值; 以及数据通信部分，被配置为与计数信号的存储值相对应地发送由传感器输出的感测数据或从另一通信装置接收的感测数据。

    MULTI-CORE PROCESSOR SYSTEM, ALLOCATION PROGRAM, CONTROL PROGRAM, ALLOCATION METHOD AND CONTROL METHOD
    15.
    发明公开
    MULTI-CORE PROCESSOR SYSTEM, ALLOCATION PROGRAM, CONTROL PROGRAM, ALLOCATION METHOD AND CONTROL METHOD 审中-公开
    多媒体广播系统，ZUWEISUNGSPROGRAMM，STEUERPROGRAMM，ZUWEISUNGSVERFAHREN UND STEERERVERFAHREN

    公开(公告)号：EP2600245A1

    公开(公告)日：2013-06-05

    申请号：EP10855322.3

    申请日：2010-07-30

    申请人： Fujitsu Limited

    发明人： YAMASHITA, Koichiro ,  SUZUKI, Takahisa ,  YAMAUCHI, Hiromasa ,  KURIHARA, Koji

    IPC分类号： G06F9/48 ,  G06F9/50

    CPC分类号： G06F13/34 ,  G06F1/324 ,  G06F1/329 ,  G06F9/4812 ,  G06F9/5033 ,  G06F13/24 ,  G06F13/26 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/24

    摘要： A CPU #0 detects an assignment instruction for a process 1. The CPU #0 acquires a remaining time obtained by subtracting a CP of a handler B (processing time of handler A) from a period (Dt of handler B) that is from the time when an event of the handler B occurs, which is interrupt processing assigned to a CPU #1. The CPU #0 judges if the acquired remaining time is greater than or equal to a processing time (CP of process 1) defined to limit an interrupt in the process. In other words, when the process 1 is assigned to the CPU #1, even if an event of the handler B occurs during execution of the process 1, the CPU #0 judges whether the Dt of the handler B can be met. When the event of the handler B occurs during execution of the process 1, the CPU #0 judges that the Dt of the handler B can be met and therefore, the CPU #0 assigns the process 1 to the CPU #1.

    摘要翻译： CPU＃0检测处理1的分配指示。CPU＃0从通过从处理器B的周期（处理器B的Dt））中减去处理器B的CP（处理器A的处理时间）获得的剩余时间 发生处理程序B的事件的时间，这是分配给CPU＃1的中断处理。 CPU＃0判断所获取的剩余时间是否大于或等于在该处理中限制中断的处理时间（处理1的CP）。 换句话说，当处理1被分配给CPU＃1时，即使在处理1的执行期间发生处理程序B的事件，CPU＃0判断是否可以满足处理程序B的Dt。 当在处理1的执行期间发生处理程序B的事件时，CPU＃0判定处理程序B的Dt可以被满足，因此CPU＃0将处理1分配给CPU＃1。

    MULTI-CORE SYSTEM AND SCHEDULING METHOD
    16.
    发明公开
    MULTI-CORE SYSTEM AND SCHEDULING METHOD 审中-公开
    多伦多大学

    公开(公告)号：EP2587374A1

    公开(公告)日：2013-05-01

    申请号：EP10853690.5

    申请日：2010-06-25

    申请人： Fujitsu Limited

    发明人： KURIHARA, Koji ,  YAMASHITA, Koichiro ,  YAMAUCHI, Hiromasa ,  SUZUKI, Takahisa

    IPC分类号： G06F9/48 ,  G06F9/52

    CPC分类号： G06F9/48 ,  G06F9/4881 ,  G06F13/366 ,  G06F2209/483 ,  G06F2209/485

    摘要： Profile information (26) concerning access of peripheral devices by tasks assigned to processor cores is prepared in advance. A monitor (27) monitors access requests to each peripheral device from the tasks under execution at the processor cores. If a task under execution at a processor core #0_(21) issues an access request to a peripheral device A(24) when a task under execution at a processor core #1_(22) has already accessed a peripheral device B(25), contention occurs at a bus. The monitor (27), therefore, prohibits the access request by the task under execution at the processor core #0_(21). A scheduler (28), based on the profile information (26), replaces the task under execution at the processor core #0_(21) with a task that does not cause contention at the bus.

    摘要翻译： 预先准备关于通过分配给处理器核心的任务来访问外围设备的简档信息（26）。 监视器（27）从处理器核心处执行的任务监视对每个外围设备的访问请求。 如果在处理器核心＃1_（22）处于执行中的任务已经访问了外围设备B（25）时，在处理器核心＃0_（21）下执行的任务向外围设备A（24）发出访问请求， 在公共汽车上发生竞争。 因此，监视器（27）禁止在处理器核心＃0_（21）处执行的任务的访问请求。 基于简档信息（26）的调度器（28）用处理器核心＃0_（21）处理执行的任务替换不在总线上引起争用的任务。

    MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD
    17.
    发明公开
    MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD 审中-公开
    多核处理器系统，控制程序和控制方法

    公开(公告)号：EP2541407A1

    公开(公告)日：2013-01-02

    申请号：EP10846491.8

    申请日：2010-02-23

    申请人： Fujitsu Limited

    发明人： YAMASHITA, Koichiro ,  YAMAUCHI, Hiromasa ,  MIYAZAKI, Kiyoshi

    IPC分类号： G06F9/50

    CPC分类号： G06F9/505

    摘要： In a multi-core processor system, applications A, C, and D are under execution, and all applications under execution are high-reliability applications. CPU 0 is allocated the high-reliability master threads of application C and application D; CPU 1 is allocated the high-reliability master thread of application A. CPU 0, which is the master CPU, by a scheduler (100), receives an allocation instruction for a low-reliability thread of application B, which is a low-reliability application, and identifies a CPU that is not allocated a high-reliability master thread. Here, CPU 2 and CPU 3 are identified and CPU 0 gives to CPU 2 identified by the scheduler (100), notification of an invocation instruction for the low-reliability thread by the scheduler (100). Thus, control is performed such that a high-reliability master thread and a low-reliability thread are not allocated to the same CPU.

    摘要翻译： 在多核处理器系统中，应用程序A，C和D正在执行中，所有正在执行的应用程序都是高可靠性应用程序。 CPU 0分配了应用程序C和应用程序D的高可靠性主线程; CPU1被分配应用A的高可靠性主线程。作为主CPU的CPU0由调度器（100）接收用于应用B的低可靠性线程的分配指令，该低可靠性线程是低可靠性的 应用程序，并识别未分配高可靠性主线程的CPU。 这里，标识CPU 2和CPU 3，并且CPU 0给由调度器（100）标识的CPU 2，调度器（100）通知用于低可靠性线程的调用指令。 因此，执行控制以使得高可靠性主线程和低可靠性线程不被分配给相同的CPU。

    COMMUNICATION DEVICE, SYSTEM, AND COMMUNICATION METHOD
    20.
    发明授权
    COMMUNICATION DEVICE, SYSTEM, AND COMMUNICATION METHOD 有权
    通信设备，系统和通信方法

    公开(公告)号：EP2892252B1

    公开(公告)日：2017-01-18

    申请号：EP12883686.3

    申请日：2012-08-28

    申请人： Fujitsu Limited

    发明人： YAMAUCHI, Hiromasa ,  YAMASHITA, Koichiro ,  SUZUKI, Takahisa ,  KURIHARA, Koji ,  OTOMO, Toshiya ,  TERANISHI, Yuta

    IPC分类号： H04W4/04 ,  H04W52/02 ,  H04W84/18

    CPC分类号： H04W52/0258 ,  H04W52/0277 ,  H04W84/18 ,  Y02D70/00

    摘要： A sensor node (101-i) is assumed to be able to execute any one among a first operation by which another sensor node (101) is requested to execute data process and if the request is not accepted the sensor node (101-i) starts executing the data processing after waiting for charging and a second operation by which the sensor node (101-i) starts executing the data processing after waiting for charging, without requesting the data processing to be executed. The sensor node (101-i) compares an expected value of a first time that elapses until execution is started by the sensor node (101-i) or the other sensor node (101) when the first operation is executed, and a second time that elapses until execution is started by the sensor node (101-i) when the second operation is executed. Based on the comparison result, the sensor node (101-i) executes among the first operation and the second operation, the operation for which the time that elapses until execution is started is shorter.