公开(公告)号：EP2107599A3

公开(公告)日：2012-11-21

申请号：EP09156243.9

申请日：2009-03-26

申请人： General Electric Company

发明人： Kapusta, Christopher James ,  Cunningham, Donald ,  Saia, Richard Joseph ,  Durocher, Kevin ,  Iannotti, Joseph ,  Hawkins, William

IPC分类号： H01L21/60 ,  B81B7/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/525

CPC分类号： H01L23/3114 ,  B81B7/007 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A system and method for forming a wafer level package (WLP) (12) (i.e., wafer level chip size package) is disclosed. The WLP (12) includes a silicon integrated circuit (IC) substrate (10) having a plurality of die pads (22) formed on a top surface thereof and a plurality of polymer laminates (16) positioned thereon. Each of the polymer laminates (16) is comprised of a separate pre-formed laminate sheet and has a plurality of vias (20) formed therein that correspond to a respective die pad (22). A plurality of metal interconnects (26) are formed on each of the plurality of polymer laminates (16) so as to cover a portion of a top surface of a polymer laminate (16) and extend down through the via (20) and into contact with a metal interconnect (26) on a neighboring polymer laminate positioned below (16). An input/output (I/O) system interconnect (34) is positioned on a top surface of the wafer level package (12) and is attached to the plurality of metal interconnects (26).

公开(公告)号：EP2268117A2

公开(公告)日：2010-12-29

申请号：EP10165655.1

申请日：2010-06-11

申请人： General Electric Company

发明人： Kapusta, Christopher James ,  Cunningham, Donald Paul

IPC分类号： H05K9/00

CPC分类号： H05K9/0043 ,  H05K9/0024 ,  Y10T29/49002

摘要： A system and method of forming a patterned conformal structure (10) for an electrical system (12) is disclosed. The conformal structure (10) includes a dielectric coating (18) positioned on an electrical system (12) having circuit components (16) mounted thereon, the dielectric coating (18) shaped to conform to a surface of the electrical system (12) and having a plurality of openings (20) therein positioned over contact pads (22) on the surface of the electrical system. The conformal structure (10) also includes a conductive coating (24) layered on the dielectric coating (18) and on the contact pads (22) such that an electrical connection is formed between the conductive coating (24) and the contact pads (22). The dielectric coating (18) and the conductive coating (24) have a plurality of overlapping pathway openings (27) formed therethrough to isolate a respective shielding area (26) of the conformal structure over desired circuit components (16) or groups of circuit components.

摘要翻译： 公开了一种形成用于电气系统（12）的图案化共形结构（10）的系统和方法。 保形结构（10）包括位于其上安装有电路部件（16）的电气系统（12）上的电介质涂层（18），所述电介质涂层（18）成形为符合电气系统（12）的表面，以及 其中多个开口（20）位于电气系统表面上的接触焊盘（22）上。 共形结​​构（10）还包括层叠在电介质涂层（18）上和接触焊盘（22）上的导电涂层（24），使得在导电涂层（24）和接触焊盘（22）之间形成电连接 ）。 电介质涂层（18）和导电涂层（24）具有穿过其形成的多个重叠的通路开口（27），以将所述共形结构的相应屏蔽区域（26）隔离在期望的电路部件（16）或电路组件组 。

公开(公告)号：EP2050712A2

公开(公告)日：2009-04-22

申请号：EP08166371.8

申请日：2008-10-10

申请人： General Electric Company

发明人： Aimi, Marco Francesco ,  Kapusta, Christopher James ,  Gowda, Arun Virupaksha ,  Hays, David Cecil ,  Boomhoower, Oliver Charles ,  Claydon, Glenn Scott ,  Iannotti, Joseph Alfred ,  Keimel, Christopher Fred

IPC分类号： B81C1/00

CPC分类号： B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/032 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/00

摘要： Multiple microelectromechanical systems (MEMS) on a substrate (20) are capped with a cover (28) using a layer that may function as a bonding agent, separation layer, and hermetic seal. A substrate (20) has a first side (20A) with multiple MEMS devices. A cover (28) is formed with through-holes (40) for vias (40), and with standoff posts (34) for layer registration and separation. An adhesive sheet (42) is patterned with cutouts (44) for the MEMS devices, vias (40), and standoff posts (34). The adhesive sheet (42) is tacked to the cover (28), then placed on the mems substrate (20) and heated to bond the layers. The via holes (40) may be metalized with leads for circuit board (58) connection. The mems units (22) may be diced from the substrate (20) after sealing, thus protecting them from contaminants.

摘要翻译： 使用可用作粘合剂，分离层和气密密封的层，用盖（28）将基材（20）上的多个微机电系统（MEMS）封盖。 衬底（20）具有多个MEMS器件的第一侧（20A）。 盖（28）形成有用于通孔（40）的通孔（40）和用于层对准和分离的支柱（34）。 图案化粘合片（42），用于MEMS器件，通孔（40）和支柱（34）的切口（44）。 将粘合片（42）固定到盖（28）上，然后放置在MEM基板（20）上并加热以粘合层。 通孔（40）可以用电路板（58）连接的引线金属化。 密封单元（22）可以在密封之后从基板（20）切割，从而保护它们免受污染。