-
11.发明公开
公开(公告)号：EP0929101A1
公开(公告)日：1999-07-14
申请号：EP98310525.5
申请日：1998-12-21
发明人： Bronner, Gary Bela , Gambino, Jeffrey P. , Mandelman, Jack A. , Radens, Carl J. , Tonti, William Robert
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/28 , H01L21/225
CPC分类号： H01L21/28035 , H01L21/82345
摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.
摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选择数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些栅极结构，从而提供双功能掺杂 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，由此各个栅极结构在其顶部部分包含自对准绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。
-
公开(公告)号：EP0987765A3
公开(公告)日：2000-11-29
申请号：EP99113439.6
申请日：1999-07-10
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried- strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
-
13.发明公开DRAM trench capacitor and method of fabricating the same 审中-公开Graben-KondensatorfürDRAM und Verfahren zur Herstellung desselben
公开(公告)号：EP0962972A1
公开(公告)日：1999-12-08
申请号：EP99304168.0
申请日：1999-05-28
发明人： Economikos, Laertis , Gruening, Ulrike , Ho, Herbert L. , Radens, Carl J. , Jammy, Ragarao , Hoepfner, Joachim , Shen, Hua
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A storage node for deep trench-based storage capacitor is formed by etching a trench (11) in a surface of a semiconductor substrate (10), forming a layer of dielectric (14) on a sidewall of the trench, partially removing the layer of dielectric material in order to expose an upper portion of the sidewall, growing a layer of oxide (16) on the upper portion of the sidewall, removing the remainder of the layer of dielectric material, doping to form a buried plate (17), forming a node dielectric (18), and forming an inner electrode (19) within the trench. The oxide layer at the upper portion of the trench is preferably formed by a LOCOS technique.
摘要翻译： 通过在半导体衬底（10）的表面上蚀刻沟槽（11）形成用于深沟槽存储电容器的存储节点，在沟槽的侧壁上形成电介质层（14），部分地去除 电介质材料以暴露侧壁的上部，在侧壁的上部生长一层氧化物（16），去除电介质材料层的其余部分，掺杂以形成掩埋板（17），形成 节点电介质（18），并且在所述沟槽内形成内部电极（19）。 沟槽上部的氧化物层优选通过LOCOS技术形成。
-
14.发明公开
公开(公告)号：EP1032040A3
公开(公告)日：2001-11-21
申请号：EP00103742.3
申请日：2000-02-23
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译： 集成电路具有初级器件，并且冗余器件通过至少一个保险丝选择性地代替初级器件。 熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。
-
公开(公告)号：EP0987765A2
公开(公告)日：2000-03-22
申请号：EP99113439.6
申请日：1999-07-10
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried- strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
摘要翻译： 本发明涉及制造半导体存储器结构的工艺，特别是深沟槽半导体存储器件，其中将温度敏感的高介电常数材料并入电容器的存储节点中。 具体地，本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。 该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。 此外，本发明的方法限制了埋层扩散的程度，从而改善阵列MOSFET的电气特性。
-
16.发明公开Low-resistance salicide fill for trench capacitors 有权Salizidfüllungmit niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A3
公开(公告)日：2003-08-20
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide (32) as a component of the trench electrode (26,32,34) in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
-
公开(公告)号：EP1032040A2
公开(公告)日：2000-08-30
申请号：EP00103742.3
申请日：2000-02-23
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
-
18.发明授权Method of providing low-resistance salicide fill for trench capacitors 有权一种用于电容器严重Salizidfüllung低电阻过程
公开(公告)号：EP0967643B1
公开(公告)日：2006-12-13
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
-
19.发明公开Low-resistance salicide fill for trench capacitors 有权Verfahren zurSalizidfüllungmit Niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A2
公开(公告)日：1999-12-29
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.013 秒)
