公开(公告)号：EP3231088B1

公开(公告)日：2020-07-22

申请号：EP15797226.6

申请日：2015-11-06

申请人： Qualcomm Incorporated

发明人： TAGHIVAND, Mazhareddin ,  RAJAVI, Yashar ,  KHALILI, Alireza

IPC分类号： H03H11/24

公开(公告)号：EP3039717B1

公开(公告)日：2018-12-12

申请号：EP14759424.6

申请日：2014-08-22

申请人： Qualcomm Incorporated

发明人： VAHID FAR, Mohammad, B. ,  KHALILI, Alireza ,  WANG, Cheng-Han ,  CHEN, Phoebe, Peihong

IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02 ,  H02M3/00 ,  H02M3/18

CPC分类号： H01L29/94 ,  H01L27/0805 ,  H01L27/0811 ,  H02M3/00 ,  H02M3/18

摘要： A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

公开(公告)号：EP3251220B1

公开(公告)日：2018-08-01

申请号：EP15820967.6

申请日：2015-12-16

申请人： Qualcomm Incorporated

发明人： RAJAVI, Yashar ,  KHALILI, Alireza ,  ADNAN, Muhammad

IPC分类号： H04B1/403 ,  H04W52/02

CPC分类号： H04W52/028 ,  H04B1/403 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/40

摘要： An analog front-end (AFE) for a communications device includes a low-power frequency synthesizer with reduced footprint. The AFE includes a first frequency synthesizer and a second frequency synthesizer. The first frequency synthesizer is coupled to a transmit (TX) chain and to a receive (RX) chain of the AFE. The first frequency synthesizer is to generate a first local oscillator (LO) signal for transmitting or receiving carrier signals when the device is in a normal operating mode. The second frequency synthesizer is coupled to the RX chain and shares one or more components of the TX chain. The second frequency synthesizer is to utilize the one or more shared components to generate a second LO signal for receiving carrier signals when the device operates in a low-power mode. For example, the one or more shared components may include a voltage source and/or one or more inductors.

公开(公告)号：EP3192181B1

公开(公告)日：2018-03-28

申请号：EP15754075.8

申请日：2015-08-11

申请人： Qualcomm Incorporated

发明人： KHALILI, Alireza ,  TAGHIVAND, Mazhareddin ,  KEERTI, Arvind

IPC分类号： H03B5/12 ,  H03L7/099 ,  H04B1/00

CPC分类号： H03L7/099 ,  H03B5/1212 ,  H04B1/005 ,  H04B1/0064

摘要： Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

公开(公告)号：EP3231089A1

公开(公告)日：2017-10-18

申请号：EP15813214.2

申请日：2015-12-03

申请人： Qualcomm Incorporated

发明人： VAHID FAR, Mohammad Bagher ,  KHALILI, Alireza ,  RAJAVI, Yashar ,  KAVOUSIAN, Amirpouya

IPC分类号： H03K5/00 ,  H03K5/156

CPC分类号： H03K5/00006 ,  H03B19/10 ,  H03B19/14 ,  H03K5/1565

摘要： A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.

摘要翻译： 提供了一种方法，一种装置和一种计算机程序产品。 该设备根据第一时钟频率输出正弦信号，基于正弦信号产生具有25％占空比的第一数字信号，基于正弦信号产生具有25％占空比的第二数字信号， 第一数字信号和第二数字信号以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍以产生具有 第三时钟频率是第一时钟频率的四倍。 该设备还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及用于第二缓冲器的第三控制电压。

公开(公告)号：EP3127238A1

公开(公告)日：2017-02-08

申请号：EP15731480.8

申请日：2015-06-16

申请人： Qualcomm Incorporated

发明人： KAVOUSIAN, Amirpouya ,  KHALILI, Alireza ,  VAHID FAR, Mohammad Bagher

IPC分类号： H03H1/00 ,  H05K1/02 ,  H01Q1/52

CPC分类号： H03H7/0153 ,  H01Q1/52 ,  H01Q7/00 ,  H03H1/0007 ,  H03H2001/0078 ,  H04B3/28 ,  H05K1/0228 ,  H05K1/165

摘要： A method and an apparatus for canceling EM coupling are provided. The apparatus includes a ring structure at least partially surrounding an EM circuit. A negative transconductance circuit is coupled to ends of the ring structure. The negative transconductance circuit is configured to cancel an EM coupling to the EM circuit at a frequency. The method includes generating a plurality of settings for a negative transconductance circuit and tuning the negative transconductance circuit to one of the plurality of settings for the negative transconductance circuit to cancel an EM coupling to an EM circuit at a frequency.

摘要翻译： 提供了一种抵消EM耦合的方法和装置。 该装置包括至少部分地围绕EM电路的环形结构。 负跨导电路耦合到环结构的端部。 负跨导电路被配置为以一个频率消除与EM电路的EM耦合。 该方法包括产生用于负跨导电路的多个设置，并将负跨导电路调谐到用于负跨导电路的多个设置中的一个设置以消除以一频率对EM电路的EM耦合。