公开(公告)号：EP0174048A1

公开(公告)日：1986-03-12

申请号：EP85201371.3

申请日：1985-08-30

申请人： Philips Electronics N.V.

发明人： De Troye, Nicolaas Cornelis

IPC分类号： G06F7/552

CPC分类号： G06F7/5525

摘要： The invention relates to a root extraction circuit comprising a plurality of n sub circuits, the m th sub-circuit thereof consisting of m+ add/subtract cells. The two add/subtract cells in each sub circuit which process the least-significant bits in said sub-circuit always receive a logic signal "1" on their "b" data input and always operate as an add cell. The remaining add/subtract cells of an m'" sub-circuit are controlled by the carry signal output of the add/subtract cell which processes the most-significant bit in the (k-1) th sub-circuit. As a result of the foregoing steps, the root extraction circuit requires only add/subtract cells, so that a very regular lay-out pattern can be obtained when the circuit is integrated.

摘要翻译： 本发明涉及包括多个n个子电路的根提取电路，其第m个子电路由m + 1个加/减单元组成。 处理所述子电路中的最低有效位的每个子电路中的两个加/减单元总是在其“b”数据输入端上接收逻辑信号“1”，并且总是作为加法单元工作。 第m个子电路的剩余加/减单元由处理第（k-1）子电路中最高有效位的加/减单元的进位信号输出控制。 作为上述步骤的结果，根提取电路仅需要加/减单元，使得当电路集成时可以获得非常规则的布局图案。

公开(公告)号：EP1884859A3

公开(公告)日：2017-07-19

申请号：EP07111660.2

申请日：2007-07-03

申请人： Vivante Corporation

发明人： Cai, Mike M. ,  Zhong, Lefan

IPC分类号： G06F1/035 ,  G06F7/556 ,  G06F7/552

CPC分类号： G06F7/60 ,  G06F1/0356 ,  G06F7/5525 ,  G06F7/556 ,  G06F2101/08 ,  G06F2101/10 ,  G06F2101/12

摘要： Methods and apparatus are provided for computing mathematical functions comprising a single pipeline for performing a polynomial approximation (e.g. a quadratic polynomial approximation, or the like), and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes, wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes.

摘要翻译： 提供了用于计算数学函数的方法和设备，所述数学函数包括用于执行多项式近似（例如二次多项式近似等）的单个管线以及与RCP，SQRT，EXP或LOG中的至少一个相对应的一个或多个数据表 可操作以根据一个或多个操作码耦合到单个管线的功能，其中单个管线可操作用于根据一个或多个操作码来计算RCP，SQRT，EXP或LOG功能中的至少一个。

公开(公告)号：EP1672481A1

公开(公告)日：2006-06-21

申请号：EP05027390.3

申请日：2005-12-14

申请人： NEC Corporation

发明人： Uesugi, Takahiko

IPC分类号： G06F7/552 ,  G06F7/52 ,  G06F7/48

CPC分类号： G06F7/5525 ,  G06F7/4824 ,  G06F7/4873

摘要： A division and square root arithmetic unit carrying out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis of a radix of an operation) of data selected from upper bits of the output of a carry save adder and the output of the adder are input to convert the data into twos complement representation data, and the twos complement representation data is shifted a certain bit number (determined on the basis of the radix of the operation) to use the shifted data for a partial remainder of the next digit. Hence, a large number of parts such as registers of a divisor and a partially extracted square root can be commonly used in a divider and a square root extractor to realize an effective and high performance arithmetic unit. Further, a radix of a division operation can be set higher than that of a square root extraction operation, and division processing performance can be largely improved. Further, in the square root extraction operation, the partial remainder previously shifted 1 bit to the right is prepared, and another partial remainder is operated from the 1 bit shifted partial remainder to set the shift bit number to the same as 2 bits shift to the left for the division operation. Hence, the twos complement converter can be commonly used in the division operation and the square root extraction operation without adding the selector in the return path of the data. Therefore, the lowering of the processing speed in the division operation and the square root extraction operation can be prevented in the division and square root arithmetic unit of the present invention.

摘要翻译： 执行较低基数的较高基数和平方根提取操作的除法运算的除法和平方根算术单元。 输入从进位存储加法器的输出的高位和加法器的输出中选择的数据的某个位数（基于操作的基数确定），以将数据转换成二进制补码表示数据，并且 二进制补码表示数据被移位一定比特数（基于操作的基数确定），以使用移位的数据用于下一个数字的部分余数。 因此，分割器和平方根提取器中可以通常使用诸如除数寄存器和部分提取的平方根的大量部件来实现有效和高性能的算术单元。 此外，可以将除法运算的基数设置为高于平方根提取操作的基数，并且可以大大提高分割处理性能。 此外，在平方根提取操作中，准备了向右移位1位的部分余数，并且从1位移位的部分余数中操作另一部分余数，以将移位位数设置为相同于2位移位到 留给分区操作。 因此，二进制补码转换器可以在分割操作和平方根提取操作中常用，而不在数据的返回路径中添加选择器。 因此，可以在本发明的分割和平方根算术单元中防止分割运算中的处理速度的降低和平方根提取操作。

公开(公告)号：EP0416309B1

公开(公告)日：1999-01-13

申请号：EP90115266.0

申请日：1990-08-09

申请人： CYRIX CORPORATION

发明人： Briggs, Willard Stuart ,  Brightman, Thomas B. ,  Matula, David William

IPC分类号： G06F7/552

CPC分类号： G06F7/5525

公开(公告)号：EP0461214B1

公开(公告)日：1997-08-06

申请号：EP90917368.4

申请日：1990-11-13

申请人： MOTOROLA, INC.

发明人： LINDSLEY, Brett, Louis

IPC分类号： G06F7/38

CPC分类号： G06F7/5525 ,  G06F2207/5521

摘要： A method and apparatus is disclosed that utilizes ''Lindsley's Law'', a polynomial convergence algorithm, suitable even for high convergence rates, to implement more efficient reciprocal jth root, and hence, jth root itself, computations of desired inputs. The invention emphasizes multiplication (114, 116, 118, 120), instead of addition, as the iterative operator, thereby reducing error at a rate relative to a power of a selected convergence rate.

公开(公告)号：EP0395240B1

公开(公告)日：1997-06-18

申请号：EP90303654.9

申请日：1990-04-05

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Steiss, Donald E. ,  Hipona, Maria B. ,  Darley, Henry M.

IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/48

CPC分类号： G06F7/5324 ,  G06F7/535 ,  G06F7/5525 ,  G06F7/57 ,  G06F2207/382 ,  G06F2207/5355

公开(公告)号：EP0723218A3

公开(公告)日：1996-07-31

申请号：EP96103447.7

申请日：1990-10-16

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Taniguchi, Takashi

IPC分类号： G06F7/02

CPC分类号： G06F7/535 ,  G06F7/026 ,  G06F7/4873 ,  G06F7/49952 ,  G06F7/49957 ,  G06F7/544 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

摘要： An approximate solution Ya of a function F with respect to a given value X is derived by referring to a relation Y=F(X) at an accuracy at which an error between the approximate solution Ya and an infinitely precise solution Y is smaller than a weight of a digit in a place lower than a lowest place of significant digits for a final solution by two places. The approximate solution Ya is rounded to an interim solution Yr equal to one of possible interim solutions which is closest to the approximate solution Ya. A value Xr is derived from the interim solution Yr and an inverse function F -1 by referring to a relation Xr=F -1 (Yr) . A sticky digit S is set to 0, 1, or -1 in response to the relation between the magnitudes of the values X and Xr and other information. The sticky digit S is added to a place immediately lower than a lowest place of the interim solution Yr. A result of this addition is rounded in a designated rounding mode to obtain the final solution. An apparatus may be used for multiplying two numbers and subtracting a third number from the resulting product.

摘要翻译： 关于给定值X的函数F的近似解Ya是以近似解Ya与无限精确解Y之间的误差小于α的准确度处的关系Y = F（X）导出的 一个数字在一个地方的重量低于最终解决方案的有效位数的最低位置两个地方。 近似解Ya被舍入为临时解Yr，该临时解Yr等于最接近于近似解Ya的可能临时解中的一个。 通过参考关系Xr = F-1（Yr），从临时解Yr和反函数F-1导出值Xr。 响应于值X和Xr的大小与其他信息之间的关系，粘性数字S被设置为0,1或-1。 粘性数字S被添加到紧临临时解决方案Yr的最低位置的地方。 此添加的结果在指定的舍入模式下取整以获得最终解决方案。 可以使用一种装置来乘以两个数字并从所得到的产品中减去第三个数字。

公开(公告)号：EP0603794A1

公开(公告)日：1994-06-29

申请号：EP93120528.0

申请日：1993-12-20

申请人： FUJITSU LIMITED

发明人： Kaku, Takashi, Fujitsu Ltd., 1015 Kami-kodanaka ,  Miyazawa, Hideo, Fujitsu Ltd., 1015 Kami-kodanaka

IPC分类号： G06F7/552 ,  G06F15/347

CPC分类号： G06F7/5525 ,  G06F7/4806 ,  G06F7/552 ,  G06F17/10 ,  G06F2207/5521 ,  G06F2207/5525

摘要： The method and circuit find the reciprocal value of an input vector signal. The level of the input vector signal (X + jY) is first reduced to (X + jY)/ 2 in an overflow-preventing circuit. A power calculating circuit squares and adds the components of the level-reduced input vector signal, thereby obtaining a power value (X² + Y²)/2 . An initial value of a tap value (K), which represents the reciprocal value to be found, is multiplied twice by a multiplying circuit, thereby obtaining K²(X + Y)²/2 . Further, a differential circuit obtains an error signal (ΔK) = 1/2 - K²(X² + Y²)/2 by subtraction from a reference value. An updating circuit updates the tap value (K) by adding to it the error signal (ΔK). A loop consisting of the multiplication of the tap value, differential operation, and updating of the tap value, is repeated until the error signal (ΔK) is reduced to less than or equal to a predetermined value. The tap value (K) thus obtained is the desired reciprocal value 1/√(X² + Y²) of the amplitude of the input vector signal. The method and circuit can be used for amplitude normalization in a modem, for example.

摘要翻译： 方法和电路找到输入向量信号的倒数值。 在溢出防止电路中，输入矢量信号（X + jY）的电平首先降低到（X + jY）/ 2。 功率计算电路对电平降低输入矢量信号的分量进行平方并相加，从而获得功率值（X 2 + Y 2）/ 2。 通过乘法电路将代表要发现的倒数值的抽头值（K）的初始值相乘2次，从而获得K 2（X + Y）2/2。 此外，差分电路通过从参考值减法来获得误差信号（DELTA K）= 1/2-K 2（X 2 + Y 2）/ 2。 更新电路通过向其加上误差信号（DELTA K）来更新抽头值（K）。 重复由抽头值，微分运算和抽头值的更新组成的回路，直到误差信号（DELTA K）减小到小于或等于预定值。 由此获得的抽头值（K）是输入矢量信号幅度的期望的互逆值1 / 2ROOT（X 2 + Y 2）。 例如，该方法和电路可用于调制解调器中的幅度归一化。

公开(公告)号：EP0461230A4

公开(公告)日：1993-08-18

申请号：EP91901464

申请日：1990-12-03

申请人： MOTOROLA, INC.

发明人： LINDSLEY, BRETT, LOUIS

IPC分类号： G06F7/537 ,  G06F7/483 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/4873 ,  G06F7/5525 ,  G06F2207/5355

摘要： A high-speed processor utilizes combinational logic and range limitation for a modified input value to increase efficiency in convergence factor determination for convergent division and square root computation. An input value (101) is modified to a value in a limited range (104), which is then partitioned into two subdivisions (106, 108). By utilizing these two groupings, the processing platform minimizes time consumption in conversion factor determination by inverting selected binary bits to form a modified factor (114) and utilizes that modified factor to facilitate high-speed convergence factor computation.

公开(公告)号：EP0394499A4

公开(公告)日：1993-02-24

申请号：EP89912134

申请日：1989-11-02

申请人： HITACHI, LTD. ,  HITACHI ENGINEERING CO., LTD.

发明人： NARITA, MASAHISA ,  KAZIWARA, HISASHI ,  ASAI, TAKESHI ,  MORINAGA, SHIGEKI ,  KIDA, HIROYUKI ,  WATABE, MITSURU ,  NAKAMIKAWA, TETSUAKI ,  KAWASAKI, SHUNPEI ,  TATEZAKI, JUNICHI ,  NAKAGAWA, NORIO ,  KASHIWAGI, YUGO

IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/57

CPC分类号： G06F7/57 ,  G06F7/4873 ,  G06F7/49957 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/3816 ,  G06F2207/5355 ,  G06F2207/5356

摘要： An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtractor and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.