公开(公告)号：EP1137012A3

公开(公告)日：2003-09-03

申请号：EP01106031.6

申请日：2001-03-12

申请人： MICROCHIP TECHNOLOGY INC.

发明人： Gerber, Donald S. ,  Shields, Jeffrey ,  Hewitt, Kent D. ,  Davies, David M

IPC分类号： G11C16/10 ,  G11C16/14

CPC分类号： G11C16/3427 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418 ,  G11C2216/28

摘要： A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.

公开(公告)号：EP0558404A3

公开(公告)日：2000-10-11

申请号：EP93400468.0

申请日：1993-02-24

申请人： SONY CORPORATION

发明人： Arakawa, Hideki

IPC分类号： H01L27/115 ,  H01L29/788 ,  G11C16/06 ,  G11C16/04

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C2216/28 ,  H01L27/115 ,  H01L29/7883

摘要： The nonvolatile semiconductor memory uses a single floating gate transistor, wherein a control gate electrode (8) is negatively biased while a source region (2) is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate (5) into the source region through Fowler-Nordheim tunneling. And an erasing operation is performed by injecting channel hot electrons from the drain region (3) into the floating gate, or by injecting electrons from a substrate into the floating gate through Fowler-Nordheim tunneling. The source region is connected to an individual bit line, and the drain region to a common line so that over-erasing is averted.

公开(公告)号：EP0862184A3

公开(公告)日：1999-08-18

申请号：EP98301296.4

申请日：1998-02-23

申请人： SHARP KABUSHIKI KAISHA

发明人： Ohta, Yoshiji

IPC分类号： G11C16/06

CPC分类号： G11C16/3445 ,  G11C8/10 ,  G11C16/344 ,  G11C2216/28

摘要： A verify operation is accurately collectively executed on all memory cells. In verify operation, first, the levels of a pre-charge signal φpre and a collective erase verify mode selection signal φaev are made to be "L", so that a common bit line 5 and all bit lines BL0 through BLm are individually charged with a pre-charge voltage Vpre. Thereafter, the level of the collective erase verify mode selection signal φaev is made to be "H" to connect the common bit line 5 to all the bit lines BL0 through BLm and a sense amplifier 8, and all word lines WL0 through WLn are selected by a row decoder circuit 2. Then, there is watched an event that the common bit line 5 is discharged and an output signal OUT of the sense amplifier 8 becomes "L" due to the existence of a non-erased memory cell in a memory cell array 1. In this case, the discharge of the common bit line 5 occurs when at least one non-erased memory cell transistor MT exists in the memory cell array 1, and therefore, the verify operation can be accurately collectively executed on all the memory cells.

公开(公告)号：EP0429720A1

公开(公告)日：1991-06-05

申请号：EP89203052.9

申请日：1989-12-01

申请人： Philips Electronics N.V.

发明人： Vollebregt, Franciscus Hendricus Albertus ,  Cuppens, Roger

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3477 ,  G11C16/0416 ,  G11C16/3468 ,  G11C2216/28

摘要： An EEPROM, for instance a flash-EEPROM, is disclosed wherein the write-voltages and the erase-voltages to be applied have been interchanged in comparison with prior art memories.
Consequently, the developing of normally-on memory-cell-­transistors due to over-charging is prevented in the erase mode. In the write mode the over-charging-problem can be dealt with elegantly. Higher densities can be achieved and, as the operation is based on the tunneling in the write mode as well as in the erase mode, an on-chip high voltage generation will suffice.

摘要翻译： 公开了一种EEPROM，例如闪存EEPROM，其中与现有技术存储器相比，要施加的写电压和擦除电压已经互换。 因此，在擦除模式下，防止由于过充电而导致的常开存储单元晶体管的发展。 在写入模式下，过充电问题可以优雅地处理。 可以实现更高的密度，并且由于操作基于写入模式以及擦除模式中的隧穿，因此片上高电压产生就足够了。