公开(公告)号：EP2247047A1

公开(公告)日：2010-11-03

申请号：EP09159216.2

申请日：2009-04-30

申请人： EqcoLogic N.V.

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L25/02

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises:
an input port (204) for receiving a low bitrate input data signal (101),
an output port (202) for delivering a high bitrate output data signal (102),
a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105),
a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and
a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202).
The transceiver circuit (212) may be incorporated in a transceiver (200).

公开(公告)号：EP2506514B1

公开(公告)日：2014-07-23

申请号：EP12174398.3

申请日：2009-04-30

申请人： EqcoLogic NV

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L5/14 ,  H04L25/02 ,  H04B3/54

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises: an input port (204) for receiving a low bitrate input data signal (101), an output port (202) for delivering a high bitrate output data signal (102), a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105), a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202). The transceiver circuit (212) may be incorporated in a transceiver (200).

公开(公告)号：EP2506514A1

公开(公告)日：2012-10-03

申请号：EP12174398.3

申请日：2009-04-30

申请人： EqcoLogic NV

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L25/02 ,  H04B3/54

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises:
an input port (204) for receiving a low bitrate input data signal (101),
an output port (202) for delivering a high bitrate output data signal (102),
a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105),
a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and
a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202).
The transceiver circuit (212) may be incorporated in a transceiver (200).

公开(公告)号：EP0289560B1

公开(公告)日：1992-04-15

申请号：EP87907388.0

申请日：1987-10-19

申请人： NCR INTERNATIONAL INC.

发明人： LAUFFER, Donald, Keith ,  MILBY, Gregory, Howard ,  ROSTEK, Paul, Michael ,  SANWO, Ikuo, Jimmy

IPC分类号： H04L5/14

CPC分类号： H04L5/1407

摘要： A terminator for a first transceiver device (10) for transmitting data signals to and receiving data signals from a second transceiver device (12) over a transmission line (14) therebetween includes a transmitter (30, 31) coupled to the transmission line (14) for transmitting data signals to the second transceiver device (12), a receiver (30, 31) coupled to the transmission line (14) for receiving data signals from the second transceiver device (12), a termination resistor (RT1) coupled to the transmission line (14) for improving the transmission characteristics of the transmission line (14), and a switch device (38) located between the termination resistor (RT1) and the transmission line (14). The switch device (38) is closed for a portion of the time when the receiver (30, 31) is receiving data signals from the second transceiver device (12) such that when it is closed, the termination resistor (RT1) is connected to the transmission line (14), and is open for the remainder to the time such that when it is open the termination resistor (RT1) is not connected to the transmission line (14).

公开(公告)号：EP0342273A1

公开(公告)日：1989-11-23

申请号：EP88121058.7

申请日：1988-12-16

申请人： Landis & Gyr Business Support AG

发明人： Reber, Jürg

IPC分类号： H04L5/14 ,  H04L12/28

CPC分类号： H04L12/40039 ,  H04L5/1407 ,  H04L12/40

摘要： Ein Busabschluß (4) enthält einen Busabschlußwiderstand (7) und eine aus zwei Gleichrichtern (12, 13) und zwei Kondensatoren (11, 14) aufgebaute Kaskadenschaltung, mit der aus der wechselnden Spannungsdifferenz zwischen einer ersten Busleit­ung (1) und einer zweiten Busleitung (2) eine Gleichspannung gewonnen und gespeichert wird, die dazu dient, einen Bus (3) in einem definierten Zustand zu halten, wenn keiner der am Bus (3) angeschlossenen Sender aktiv ist. Ein solcher Busabschluß (4) verhindert das Auftreten eines undefinierten Buszustands bei Anwendung solcher Datenverkehrs-Protokolle, bei denen auf dem Bus (3) so regelmäßig Datenverkehr abgewickelt wird, daß die Zeitspannen, in denen keiner der am Bus (3) angeschlossenen Sender aktiv ist, zwangsläufig begrenzt sind.

摘要翻译： 总线终端（4）包含总线终端电阻（7）和由两个整流器（12,13）和两个电容器（11,14）构成的级联电路，通过该电路从交流电压差获得直流电压 在第一总线（1）和第二总线（2）之间存储，用于将总线（3）保持在与总线（3）连接的发送机没有活动的限定状态下。 这种总线终端（4）在使用其中在总线（3）上处理数据业务的这种数据业务协议时，防止发生未定义的总线状态，其规律性在于，没有发送器连接到总线 （3）是有限的活动。

公开(公告)号：EP0289560A1

公开(公告)日：1988-11-09

申请号：EP87907388.0

申请日：1987-10-19

申请人： NCR CORPORATION

发明人： LAUFFER, Donald, Keith ,  MILBY, Gregory, Howard ,  ROSTEK, Paul, Michael ,  SANWO, Ikuo, Jimmy

IPC分类号： H04L5

CPC分类号： H04L5/1407

摘要： Un termineur d'un premier dispositif émetteur-récepteur (10) qui transmet des signaux de données à un deuxième dispositif émetteur-récepteur (12) et reçoit des signaux émis par ce dernier par une ligne de transmission (14) s'étendant entre les deux comprend un émetteur (30, 31) couplé à la ligne de transmission (14) afin de transmettre des signaux de données au deuxième dispositif émetteur-récepteur (12), un récepteur (30, 31) couplé à la ligne de transmission (14) afin de recevoir des signaux de données du deuxième dispositif émetteur-récepteur (12), une résistance de terminaison (RT1) couplée à la ligne de transmission (14) afin d'améliorer les caractéristiques de transmission de la ligne de transmission (14), et un dispositif commutateur (38) situé entre la résistance de terminaison (RT1) et la ligne de transmission (14). Le dispositif commutateur (38) est fermé pendant une partie du temps, pendant que le récepteur (30, 31) reçoit des signaux de données émis par le deuxième dispositif émetteur-récepteur (12), de sorte que lorsqu'il est fermé, la résistance de terminaison (RT1) soit connectée à la ligne de transmission (14), et est ouvert pendant le reste du temps, de sorte que lorsqu'il est ouvert la résistance de terminaison (RT/) ne soit pas connectée à la ligne de transmission (14).

公开(公告)号：EP2451130B1

公开(公告)日：2014-07-16

申请号：EP12153028.1

申请日：2009-04-30

申请人： EqcoLogic N.V.

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L5/14 ,  H04B3/54

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises: an input port (204) for receiving a low bitrate input data signal (101), an output port (202) for delivering a high bitrate output data signal (102), a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105), a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202). The transceiver circuit (212) may be incorporated in a transceiver (200).

摘要翻译： 一种用于从单端传输介质（105）传输低比特率数据信号（177）和接收高比特率数据信号（166R）的主动收发器电路（212），所述传输介质（105）包括内部导体 （107）和导电屏蔽层（109），包括：用于接收低比特率输入数据信号（101）的输入端口（204），用于传送高比特率输出数据信号（102）的输出端口（202） 差分输入/输出端口（203），用于将低比特率数据信号（177）发射到单端传输介质（105）中并用于从单端传输介质（105）接收高比特率数据信号（166R）; 第一和第二单端输出驱动器（191,192），适于在其各自的输出节点（111,112）上递送低比特率输入数据信号（101），其被形成为至少5倍的最大转换速率 高于接收到的高比特率数据信号（166R）的最大转换速率，a 以及用于在所述第一和第二单端输出驱动器（191,192）的输出节点（111,112）处接收所述信号的高比特率接收器（117），并且用于在所述输出端上产生高比特率输出数据信号（102） 端口（202）。 收发器电路（212）可以并入收发器（200）中。

公开(公告)号：EP2648378A1

公开(公告)日：2013-10-09

申请号：EP13174528.3

申请日：2009-04-30

申请人： EqcoLogic N.V.

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L25/02 ,  H04B3/54

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： A communication system includes at least one transceiver circuit (212, 412) and a single ended transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109). The inner conductor (107) is coupled to the transceiver circuit (212, 412) by means of a first transmission line (121, 321), and the conductive shield layer (109) of the transmission medium (105) is coupled to the transceiver circuit (212, 412) by means of a second transmission line (122, 322). A first impedance (Z1, Z3) comprising at least one ferrite bead is coupled to the first transmission line (121, 321) for device power communication.

摘要翻译： 通信系统包括至少一个收发器电路（212,412）和包括内部导体（107）和导电屏蔽层（109）的单端传输介质（105）。 内导体（107）借助于第一传输线（121,321）耦合到收发器电路（212,412），并且传输介质（105）的导电屏蔽层（109）耦合到收发器 电路（212,412），借助于第二传输线（122,322）。 包括至少一个铁氧体磁珠的第一阻抗（Z1，Z3）被耦合到第一传输线（121,321），用于设备电力通信。

公开(公告)号：EP2247047B1

公开(公告)日：2013-08-21

申请号：EP09159216.2

申请日：2009-04-30

申请人： EqcoLogic N.V.

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L25/02

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises: an input port (204) for receiving a low bitrate input data signal (101), an output port (202) for delivering a high bitrate output data signal (102), a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105), a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202). The transceiver circuit (212) may be incorporated in a transceiver (200).

摘要翻译： 一种用于从单端传输介质（105）传输低比特率数据信号（177）和接收高比特率数据信号（166R）的主动收发器电路（212），所述传输介质（105）包括内部导体 （107）和导电屏蔽层（109），包括：用于接收低比特率输入数据信号（101）的输入端口（204），用于传送高比特率输出数据信号（102）的输出端口（202） 差分输入/输出端口（203），用于将低比特率数据信号（177）发射到单端传输介质（105）中并用于从单端传输介质（105）接收高比特率数据信号（166R）; 第一和第二单端输出驱动器（191,192），适于在其各自的输出节点（111,112）上递送低比特率输入数据信号（101），其被形成为至少5倍的最大转换速率 高于接收到的高比特率数据信号（166R）的最大转换速率，a 以及用于在所述第一和第二单端输出驱动器（191,192）的输出节点（111,112）处接收所述信号的高比特率接收器（117），并且用于在所述输出端上产生高比特率输出数据信号（102） 端口（202）。 收发器电路（212）可以并入收发器（200）中。

公开(公告)号：EP2451130A1

公开(公告)日：2012-05-09

申请号：EP12153028.1

申请日：2009-04-30

申请人： EqcoLogic N.V.

发明人： Devuyst, Bram ,  Kuijk, Maarten

IPC分类号： H04L25/02 ,  H04B3/54

CPC分类号： H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

摘要： A communication system includes at least one transceiver circuit (212, 412) and a single ended transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109). The inner conductor (107) is coupled to the transceiver circuit (212, 412) by means of a first transmission line (121, 321), and the conductive shield layer (109) of the transmission medium (105) is coupled to the transceiver circuit (212, 412) by means of a second transmission line (122, 322). A first impedance (Z1, Z3) comprising at least one ferrite bead is coupled to the first transmission line (121, 321) for device power communication.