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    FLOATING POINT ADDER
    11.
    发明公开
    FLOATING POINT ADDER 审中-公开

    公开(公告)号：EP4184311A1

    公开(公告)日：2023-05-24

    申请号：EP22207747.1

    申请日：2022-11-16

    申请人： Imagination Technologies Limited

    发明人： Freiburghaus, Max

    IPC分类号： G06F7/485

    摘要： An adder and a method for calculating 2 n + x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2 n + x for x n -1 ≤ |x| n +1 ; a second path configured to calculate 2 n + x for |x| n ; a third path configured to calculate 2 n + x for |x| ≥ 2 n ; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.

    APPARATUS AND METHOD FOR PROCESSING FLOATING-POINT NUMBERS
    14.
    发明公开
    APPARATUS AND METHOD FOR PROCESSING FLOATING-POINT NUMBERS 审中-公开

    公开(公告)号：EP3767454A1

    公开(公告)日：2021-01-20

    申请号：EP20186217.4

    申请日：2020-07-16

    申请人： Imagination Technologies Limited

    发明人： ELLIOTT, Sam ,  KÄLLÉN, Jonas ,  VAN BENTHEM, Casper

    IPC分类号： G06F7/485 ,  G06F7/509

    摘要： Adder circuits and associated methods are disclosed, for processing a set of at least three floating-point numbers to be added together. The method comprises identifying (606), from among the at least three numbers, at least two numbers that have the same sign - that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together (608) using one or more same-sign floating-point adders (120, 220a, 320, 420). A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.

    INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD
    17.
    发明公开
    INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD 审中-公开
    用于执行矢量饱和双字/四字添加的指令和逻辑

    公开(公告)号：EP3238031A1

    公开(公告)日：2017-11-01

    申请号：EP15873977.1

    申请日：2015-11-23

    申请人： Intel Corporation

    发明人： OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  TOLL, Bret L. ,  CORBAL SAN ADRIAN, Jesus ,  CHARNEY, Mark J. ,  GIRKAR, Milind B.

    IPC分类号： G06F9/30 ,  G06F7/485

    CPC分类号： G06F9/30036 ,  G06F7/00 ,  G06F9/3001 ,  G06F9/30018

    摘要： In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

    摘要翻译： 在若干实施例中，指令集体系结构的向量扩展包括执行饱和有符号和无符号整数加法的指令。 在一个实施例中，提供了带符号饱和的矢量有符号整数加法。 在一个实施例中，提供了具有无符号饱和度的矢量无符号整数加法。 在一个实施例中，对于有符号和无符号指令都支持打包的双字和四字整数。

    COMPUTING APPARATUS FOR PROOF OF WORK, AND ASIC CHIP AND COMPUTING METHOD FOR PROOF OF WORK
    19.
    发明公开
    COMPUTING APPARATUS FOR PROOF OF WORK, AND ASIC CHIP AND COMPUTING METHOD FOR PROOF OF WORK 审中-公开

    公开(公告)号：EP4276598A1

    公开(公告)日：2023-11-15

    申请号：EP22755473.0

    申请日：2022-01-12

    申请人： Bitmain Technologies Inc.

    发明人： WU, Xufeng ,  YANG, Cunyong ,  ZHAN, Ketuan

    IPC分类号： G06F7/485

    摘要： A computing apparatus and method for proof of work, and a chip are provided, to improve the computing efficiency of proof of work. The computing apparatus comprises: N selectors, respectively configured to obtain N groups of first input quantities; and N first compressors, respectively connected to the N selectors, and respectively configured to receive the N groups of first input quantities sent by the N selectors, and to receive a same second input quantity, wherein each first compressor is configured to sequentially perform compression processing on the second input quantity and each first input quantity in one group of first input quantities, and compression processing results of the N first compressors each are used to obtain a proof of work result.

    FLOATING-POINT NUMBER COMPUTING CIRCUIT AND FLOATING-POINT NUMBER COMPUTING METHOD
    20.
    发明公开
    FLOATING-POINT NUMBER COMPUTING CIRCUIT AND FLOATING-POINT NUMBER COMPUTING METHOD 审中-公开

    公开(公告)号：EP4220379A1

    公开(公告)日：2023-08-02

    申请号：EP20959318.5

    申请日：2020-10-31

    申请人： Huawei Technologies Co., Ltd.

    发明人： JIANG, Donglong ,  DONG, Zhenjiang ,  XIE, Huan ,  LEE, Chun Hang

    IPC分类号： G06F7/485

    摘要： A floating point number calculation circuit (100) and a floating point number calculation method are disclosed. A splitting circuit (102) included in the floating point number calculation circuit (100) splits a mantissa part of a first floating point number and a mantissa part of a second floating point number. An exponential processing circuit (104) obtains a second number of shifted bits of each mantissa part obtained after splitting. A calculation circuit (105) calculates a product of the mantissa part of the first floating point number and the mantissa part of the second floating point number based on each mantissa part obtained after splitting and the second number of shifted bits of each mantissa part obtained after splitting. The floating point number calculation circuit (100) can split a large bit-width floating point number into small bit-width floating point numbers, so that a small bit-width multiplier is used to calculate the large bit-width floating point number. The floating point number calculation circuit (100) provided in this application has small timing overheads and low hardware design costs. Therefore, calculation performance of the multiplier is appropriately used.