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    DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    3.
    发明公开
    DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    SKALARPRODUKTPROZESSOREN SOWIE VERFAHREN，SYSTEME UND ANWEISUNGENDAFÜR

    公开(公告)号：EP2798457A4

    公开(公告)日：2016-07-27

    申请号：EP11878520

    申请日：2011-12-29

    申请人： INTEL CORP

    发明人： KRISHNAN KARTHIKEYAN ,  OULD-AHMED-VALL ELMOUSTAPHA ,  CHEREPANOV VICTOR

    IPC分类号： G06F9/06 ,  G06F7/48 ,  G06F9/30 ,  G06F13/14

    CPC分类号： G06F9/3001 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30192

    摘要： A method of an aspect includes receiving a dot product instruction. The dot product instruction indicates a first source packed data including at least four data elements, indicates a second source packed data including at least eight data elements, and indicates a destination storage location. A result packed data is stored in the destination storage location in response to the dot product instruction. The result includes a plurality of data elements that each includes a dot product result. Each of the dot product results includes a sum of products of the at least four data elements of the first source packed data with corresponding data elements in a different subset of at least four data elements of the second source packed data. Other methods, apparatus, systems, and instructions are disclosed.

    摘要翻译： 一方面的方法包括接收点积指令。 点产品指令指示包括至少四个数据元素的第一源打包数据，指示包括至少八个数据元素的第二源打包数据，并且指示目的地存储位置。 响应于点积指令，结果打包数据被存储在目的地存储位置。 结果包括多个数据元素，每个数据元素包括点积结果。 每个点积结果包括第一源打包数据的至少四个数据元素与第二源打包数据的至少四个数据元素的不同子集中的对应数据元素的乘积之和。 公开了其它方法，装置，系统和指令。

    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER
    5.
    发明公开
    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER 审中-公开
    VORRICHTUNG UND VERFAHREN ZUR REVERSIERUNG UND PERMUTIERUNG VON位于EINEM MASKENREGISTER

    公开(公告)号：EP3014417A4

    公开(公告)日：2017-06-21

    申请号：EP14817656

    申请日：2014-06-17

    申请人： INTEL CORP

    发明人： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT

    IPC分类号： G06F9/06 ,  G06F9/30

    CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098

    摘要： An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

    摘要翻译： 描述了用于对掩码值执行位反转和置换的设备和方法。 例如，处理器被描述为执行指令以执行以下操作：读取存储在源掩码寄存器中的多个掩码比特，掩码比特与矢量寄存器的矢量数据元素相关联; 以及执行位反转操作以将每个屏蔽位从源屏蔽寄存器复制到目的地屏蔽寄存器，其中所述位反转操作使得来自所述源屏蔽寄存器的位在所述目的地屏蔽寄存器内反转，导致对称的镜像 原来的位排列。

    VECTOR FREQUENCY EXPAND INSTRUCTION
    7.
    发明公开
    VECTOR FREQUENCY EXPAND INSTRUCTION 审中-公开
    ANWEISUNGFÜRVEKTORERWEITERUNGSFREQUENZ

    公开(公告)号：EP2798476A4

    公开(公告)日：2016-06-29

    申请号：EP11878535

    申请日：2011-12-30

    申请人： INTEL CORP

    发明人： OULD-AHMED-VALL ELMOUSTAPHA ,  SAIR SULEYMAN ,  DOSHI KSHITIJ A ,  YOUNT CHARLES R ,  TOLL BRET L

    IPC分类号： G06F9/30 ,  G06F9/305 ,  H03M7/46

    CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  H03M7/46 ,  H03M7/6005

    摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.

    摘要翻译： 包括硬件解码单元和执行引擎单元的处理器核心。 用于解码向量频率扩展指令的硬件解码单元，其中所述向量频率压缩指令包括源操作数和目的地操作数，其中所述源操作数指定源向量寄存器，其包括一对或多对值和游程长度， 根据运行长度将其扩展为该值的运行。 执行引擎单元执行解码的向量频率扩展指令，其使得源向量寄存器中的一个或多个源数据元素的集合被扩展为包括比该源数据元素集合更多的元素的一组目的地数据元素，以及 包括在源向量寄存器中运行长度编码的至少一个相同值的运行。

    METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE
    8.
    发明公开
    METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE 审中-公开

    公开(公告)号：EP3238026A4

    公开(公告)日：2018-08-01

    申请号：EP15873962

    申请日：2015-11-23

    申请人： INTEL CORP

    发明人： JHA ASHISH ,  VALENTINE ROBERT ,  OULD-AHMED-VALL ELMOUSTAPHA

    IPC分类号： G06F9/30 ,  G06F12/02

    CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30101 ,  G06F15/8053

    摘要： An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a plurality of index values; a mask register to store a plurality of mask bits; a vector register to store a plurality of vector data elements loaded from memory; and vector index load logic to identify an index stored in the vector index register to be used for a load operation using an immediate value and to responsively combine the index with a base memory address to determine a memory address for the load operation, the vector index load logic to load vector data elements from the memory address to the vector register in accordance with the plurality of mask bits.

    FOUR-DIMENSIONAL MORTON COORDINATE CONVERSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    9.
    发明公开
    FOUR-DIMENSIONAL MORTON COORDINATE CONVERSION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开

    公开(公告)号：EP3218814A4

    公开(公告)日：2018-07-18

    申请号：EP15858739

    申请日：2015-10-14

    申请人： INTEL CORP

    发明人： EVANS ARNOLD KERRY ,  OULD-AHMED-VALL ELMOUSTAPHA

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30196 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145

    摘要： A processor includes packed data registers, a decode unit, and an execution unit. The decode unit is to decode a four-dimensional (4D) Morton coordinate conversion instruction. The 4D Morton coordinate conversion instruction is to indicate a source packed data operand that is to include a plurality of 4D Morton coordinates, and is to indicate one or more destination storage locations. The execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the decode unit decoding the 4D Morton coordinate conversion instruction, is to store one or more result packed data operands in the one or more destination storage locations. The one or more result packed data operands are to include a plurality of sets of four 4D coordinates. Each of the sets of the four 4D coordinates is to correspond to a different one of the 4D Morton coordinates.