公开(公告)号：EP3098840B1

公开(公告)日：2022-05-11

申请号：EP15880882.4

申请日：2015-07-28

Inventor： CHOI, Seung Jin ,  KIM, Hee Cheol ,  CHOI, Hyun Sic

IPC: H01L21/77 ,  H01L27/12 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/324

公开(公告)号：EP3961676A1

公开(公告)日：2022-03-02

申请号：EP21192215.8

申请日：2021-08-19

Applicant: TOKYO OHKA KOGYO CO., LTD.

Inventor： UEMATSU, Teruhiro

IPC: H01L21/308 ,  H01L21/306 ,  G03F7/004

Abstract: To provide an etching method capable of forming a hole having a small diameter or a groove having a narrow width in a substrate, using an etchant, and a photosensitive resin composition for use in the etching method. An etching method, comprising: a coating step of forming a coating film by applying a photosensitive resin composition to a substrate, an exposure step of position-selectively exposing the coating film, a developing step of developing a coating film after exposure to expose a part of the substrate and obtain a patterned cured product, an etching step of etching the substrate to form a hole or groove in the substrate, with the etching being performed in the presence of a noble metal catalyst, using the patterned cured product as a mask and an aqueous solution including a corrosive agent and an oxidizing agent as an etchant, and a stripping step of stripping a patterned cured product after the etching step, from the substrate, wherein the photosensitive-resin composition comprises a resin (A), a photosensitizer (B), and a solvent (S), and wherein the resin (A) is a novolak resin.

公开(公告)号：EP3933893A1

公开(公告)日：2022-01-05

申请号：EP20885464.6

申请日：2020-07-27

Applicant: Changxin Memory Technologies, Inc.

Inventor： ZHANG, Qiang ,  YING, Zhan

IPC: H01L21/308 ,  H01L21/8239 ,  H01L27/105

Abstract: Provided are a memory and a formation method thereof. The formation method includes: providing a substrate; forming a first mask layer on the substrate, wherein a plurality of parallel strip-shaped patterns are formed in the first mask layer and positioned above the array area, and an end of each of the strip-shaped patterns being connected to the first mask layer on the peripheral area of the substrate; forming a second mask layer on the first mask layer, wherein a plurality of first patterns are formed in the second mask layer, the plurality of first patterns are arranged in array and overlapped with the strip-shaped patterns to form division trenches in the substrate to divide the continuous active areas into a plurality of discrete active areas; and performing etching layer by layer by using the second mask layer and the first mask layer as masks to transfer the strip-shaped patterns and the first patterns into the substrate to form the discrete active areas arranged in an array. The reliability of the memory formed by the above method is improved.

公开(公告)号：EP3926662A1

公开(公告)日：2021-12-22

申请号：EP20756178.8

申请日：2020-02-13

Applicant: Tokuyama Corporation

Inventor： KIKKAWA, Yuki ,  SATO, Tomoaki ,  SHIMODA, Takafumi ,  NEGISHI, Takayuki

IPC: H01L21/306 ,  C07C211/63 ,  C07C381/12 ,  C07F9/54 ,  C09K13/04 ,  C09K13/06 ,  C23F1/40 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/768

Abstract: Provided is a treatment liquid for a semiconductor wafer or the like used in a process for forming a semiconductor. Namely a treatment liquid containing (A) a hypochlorite ion, and (B) an alkylammonium salt expressed by the following Formula (1), or the like is provided.

(In the Formula, "a" is an integer from 6 to 20; R 1 , R 2 , and R 3 are independently, for example, an alkyl group with a carbon number from 1 to 20; and X - is, for example, a chloride ion.)

公开(公告)号：EP3836235A1

公开(公告)日：2021-06-16

申请号：EP20211084.7

申请日：2020-12-01

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives

Inventor： GASSE, Adrien ,  DUSSAIGNE, Amélie ,  LEVY, François

IPC: H01L33/00 ,  H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: Procédé de réalisation d'une couche de matériau (100) structurée, comprenant :
- réalisation d'un premier substrat (102) comportant une face structurée (104) ;
- réalisation, contre la face structurée du premier substrat, d'un empilement de couches (110) comprenant une couche intermédiaire (112) et la couche à structurer, la couche intermédiaire étant disposée entre la couche à structurer et le premier substrat, une première face (114) de la couche intermédiaire disposée du côté du premier substrat étant structurée conformément à un motif inverse de celui de la face structurée du premier substrat ;
- retrait du premier substrat ;
- gravure anisotrope de la couche intermédiaire mise en œuvre depuis la première face de la couche intermédiaire, et gravure d'au moins une partie de l'épaisseur de la couche à structurer, structurant une face (119) de la couche à structurer conformément au motif de la première face de la couche intermédiaire.

公开(公告)号：EP3155643B1

公开(公告)日：2020-10-21

申请号：EP14894206.3

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： JUN, Kimin ,  MORROW, Patrick ,  NELSON, Donald

IPC: H01L21/308

公开(公告)号：EP3287495B1

公开(公告)日：2020-06-24

申请号：EP16783200.5

申请日：2016-04-20

Applicant: Toray Industries, Inc.

Inventor： FUJIWARA, Takenori ,  TANIGAKI, Yugo

IPC: C08L79/08 ,  C08L79/04 ,  G03F7/40 ,  G03F7/023 ,  G03F7/004 ,  C08F212/14 ,  C08G73/10 ,  H01L21/22 ,  H01L21/308 ,  H01L21/3205

公开(公告)号：EP2415072B1

公开(公告)日：2019-01-09

申请号：EP10719632.1

申请日：2010-04-06

Applicant: Technion Research & Development Foundation Ltd.

Inventor： TESSLER, Nir ,  BEN-SASSON, Ariel

IPC: B82Y10/00 ,  H01L27/12 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10 ,  H01L51/52 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786

公开(公告)号：EP3389083A1

公开(公告)日：2018-10-17

申请号：EP17887878.1

申请日：2017-09-22

Applicant: Mitsubishi Gas Chemical Company, Inc.

Inventor： HORITA Akinobu ,  SHIMADA Kenji ,  TAKAHASHI Kenichi ,  OIE Toshiyuki ,  ITO Aya

IPC: H01L21/308

Abstract: The present invention relates to a wet etching composition for a substrate having a SiN layer and a Si layer, comprising 0.1-50 mass% fluorine compound (A), 0.04-10 mass% oxidant (B) and water (D) and having pH in a range of 2.0-5.0. The present invention also relates to a wet etching process for a semiconductor substrate having a SiN layer and a Si layer, the process using the wet etching composition. The composition of the present invention can be used for a substrate having a SiN layer and a Si layer to enhance removal selectivity of Si over SiN while reducing corrosion of the device and the exhaust line and air pollution caused by a volatile component generated upon use and further a burden on the environment caused by the nitrogen content contained in the composition.

公开(公告)号：EP3097581B1

公开(公告)日：2018-09-19

申请号：EP14822025.4

申请日：2014-12-16

Applicant: Silicon Storage Technology Inc.

Inventor： YANG, Jeng-Wei ,  SU, Chien-Sheng

IPC: H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

Abstract: A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.