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公开(公告)号：EP0114938A3
公开(公告)日：1987-02-25
申请号：EP83110505
申请日：1983-10-21
Applicant: International Business Machines Corporation
Inventor： Patel, Arvind Motibhai
CPC classification number: H03M13/151 , G11B5/09 , H03M13/1545 , H03M13/1585
Abstract: In the multibyte error correcting system, up to t errors are correctable by processing 2t syndrome bytes. Syndrome bytes are converted into t+1 coefficients of the error locator polynomial by predetermined product operations and exclusive-OR operations involving selected syndrome bytes to produce cofactors that correspond to the desired coefficients when less then t errors occurred in the codeword. The cofactors are combined to produce coefficients when t errors occur and the correct set of coefficients are selected in accordance with the number of errors that are detected. Up to t erroneous bytes in one codeword and corrected during its transfer from the system while the next codeword is entered in the system, so that correction is on-the-fly.
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公开(公告)号：EP0053505A3
公开(公告)日：1983-07-06
申请号：EP81305641
申请日：1981-11-27
Applicant: SONY CORPORATION , KABUSHIKI KAISHA TOSHIBA
Inventor： Hoshimi, Susumu , Kojima, Tadashi
CPC classification number: G11B20/1809
Abstract: A PCM signal processing apparatus is arranged to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words. The apparatus has an error detector (16) responsive to the error detection words for detecting errors in a received transmission block and error identifying means (18, 22, 23) for identifying errors in each of the time-interleaved words included in the received transmission block which has been detected. A de-interleaver (17) is provided for time-deinterleaving each received transmission block to recover a de-interleaved block comprising de-interleaved PCM and error correction words, with errors in the de-interleaved words being respectively identified. A syndrome generating device (18) is coupled to the de-interleaver (17) for generating error syndromes using the de-interleaved PCM and error correction words in the de-interleaved block. An error correcting device (20) responsive to the error syndromes corrects erroneous PCM words in the de-interleaved block as a function of the remaining error free PCM and the error correction words in the de-interleaved block. An error compensating device (21) is responsive to the identification of errors by the error identifying device and compensates the erroneous PCM words in the de-interleaved block with a substitute PCM word when error correction by the error correcting device (20) is impossible. An inhibit device (24) inhibits the error correcting device (20) when all of the error detection words in the de-interleaved block are identified as erroneous and it discontinues inhibiting when the relationship between the identification by the error identifying device and the error syndrome indicates that no error exists.
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公开(公告)号：EP0043432A3
公开(公告)日：1982-11-03
申请号：EP81104004
申请日：1981-05-25
Applicant: International Business Machines Corporation
Inventor： Sze, Daniel Tsi Wing
IPC: H04L01/10
CPC classification number: H04L1/0057
Abstract: A synchronous data transmission system between remote stations is shown wherein data is transmitted parallel by bit serial by group over a plurality of parallel lines extending between sending and receiving stations. A parity line is also included in the transmission system for checking errors and a clock line is included by synchronization of the parallel data being transmitted. Information is transmitted from one station to another with alternating even and odd parity for succeeding groups of parallel data. The information is checked at the receiving station for even-even or odd-odd parity in succeeding groups of data. Longitudinal redundancy checking (LRC) is also added to the checking at a receiving station.
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公开(公告)号：EP0093969A3
公开(公告)日：1987-01-07
申请号：EP83104173
申请日：1983-04-28
Applicant: SONY CORPORATION
CPC classification number: H03M13/2924 , G11B20/1809 , G11B27/3063 , G11B27/34 , G11B2020/10592 , G11B2220/2545 , H03M13/15
Abstract: A method and an apparatus for error correction are disclosed. This method essentially comprises the error correction coding processing and the interleaving and de-interleaving processings for digital information data in the subchannels to be transmitted. And the apparatus comprises means for performing those processings. In more detail, the improved method for error correction of the present invention comprises the steps of: dividing digital Information data in one PACKET divided by sync signals into a plurality of PACKs as dividing units; adding a first redundant code for error detection or error correction to each of the dividing units; and interleaving the digital information data in each of the dividing units and the first redundant code for error detection or error correction; whereby the Interleaved data is transmitted together with frame sync signals and main data. The data in the subchannels is coded and Interleaved and then recorded so that the distances between the data become large. Therefore, if errors should occur, the interpolation can be properly done, thereby elevating the error correcting ability without requiring any complicated error correction circuit and any larger buffer memory such as those for the data in the main channel.
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公开(公告)号：EP0117595A3
公开(公告)日：1986-07-30
申请号：EP84200250
申请日：1984-02-22
Applicant: PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMITED , N.V. Philips' Gloeilampenfabrieken
Inventor： Sharpe, Anthony Keith , Mabey, Peter John
CPC classification number: H04W88/187 , H04L1/0057 , H04L1/0061
Abstract: In digitally encoded data transmission systems such as paging systems using a code word format, such as POCSAG, each code word includes a number of bits collectively termed the cyclic redundancy check bits. In a paging receiver the cyclic redundancy check bits are used to determine if there are errors in the received message code words. If an error is detected then one bit random error correction is generally applied because it has a more acceptable falsing rate compared to say two bit random error correction or four bit burst error correction. In a POCSAG paging system described as an example the option of one bit random error correction or a less acceptable falsing rate correction technique, such as four bit burst error correction, can be given if additional protection against falsing is provided. The additional protection is to include error detection check bits in the entire message which is transmitted by the base station. At the receiver any errors in the message code words are subjected to four bit burst error correction and thereafter the entire «corrected» message is subjected to a further check using the error detection check bits. Wether or not error detection check bits have been included in the message is indicated by preconditioning the message, for example by using predetermined ones of the plurality of addresses allocated to each pager for different purposes. If error detection check bits have not been included a more acceptable falsing rate correction technique is applied.
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Patent Agency Ranking
公开(公告)号：EP0103866A3
公开(公告)日：1986-03-05
申请号：EP83109184
申请日：1983-09-16
Applicant: NEC CORPORATION
Inventor： Nakamura, Katsuhiro
CPC classification number: H04L1/0042 , H04L27/00 , H04L27/34
Abstract: @ Disclosed is an error correction system in which part of the data bits of first multilevel input data is differentially encoded to form second data comprising the differentially encoded data bits and the remainder data bits and converting the bit patterns of the second data into third data in two-dimensional multilevel signal space according to a predetermined transfer function. A transparent error-correcting code is derived from each of the different phase of the third data and appended to each different phase to thereby form fourth data which is then modulated upon a carrier in two-dimensional multilevel signal space for transmission to a receiver where the signal is demodulated to recover the fourth data. The appended error-correcting code is separated from each different phase of the fourth data. An error which might exist in the received data is corrected by the separated error-correcting code in respect of each phase. The bit pattern of the error-corrected data is reconverted to recover the original second data. One of the phases of the second data is differentially decoded to recover the original first data.
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公开(公告)号：EP0086566A3
公开(公告)日：1985-07-10
申请号：EP83300264
申请日：1983-01-19
Applicant: SONY CORPORATION
CPC classification number: G11B20/1809 , G11B20/1833
Abstract: In an apparatus for error correction in which data sequences containing blocks each formed of plural data words previously arranged on a time-base and check words are written in a data memory (37) on the basis of a write address generator (38), the data sequences are then read out from the data memory (37) on the basis of a read address generator (39) so as to generate rearranged data sequences and, during writing and reading of the data sequences, error correction is carried out, there is included an error correction arithmetic circuit (50) for performing an error correction calculation, a pointer addition circuit (51, 52) for adding a pointer to the data words in association with an error state of the blocks, and a program memory (49) for memorizing a microprogramm with fields to control the error correction arithmetic circuit (50) and pointer addition circuit (51, 52).
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18.发明公开Regenerator for AMI coded digital signals with a tester for coding rule violations 失效用于编码规则违规的测试仪的AMI编码数字信号的再生器
公开(公告)号：EP0092215A3
公开(公告)日：1984-02-22
申请号：EP83103732
申请日：1983-04-18
Applicant: Siemens Aktiengesellschaft
Inventor： Meyer, Fritz, Dr.-Ing.
CPC classification number: H04L1/247
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公开(公告)号：EP0086482A3
公开(公告)日：1984-02-22
申请号：EP83101401
申请日：1983-02-14
Applicant: NEC CORPORATION
Inventor： Nakajima, Masahiro , Hashimoto, Hiromi
CPC classification number: H04L27/18
Abstract: The digital signal communication system comprises a transmitter and a receiver. The transmitter is provided with first means (2) for differentially converting first digital signals of n trains (n is an integer of 3 or more) to provide second digital signals of n trains comprising a plurality of words, second means (3) responsive to said second digital signals for providing a modulated signal with 2 n (= N) modulation levels and third means (4) for transmitting said modulated signal. The receiver comprises fourth means (5) for receiving said modulated signal, fifth means (6) for demodulating the output from said fourth means (5) to provide third digital signals of n trains corresponding to said second digital signals, and sixth means (7) for differentially converting said third digital signals of n trains to provide fourth digital signals of n trains corresponding to said first digital signals. The Hamming distance between two words of the second digital signal corresponding to the adjacent two modulation levels is either 1 or2 and each of the Hamming distance of 1 and that of 2 is equal to N/2. This system is not impaired even if differential logic conversion is effected, which can effect parity checking of all the bits. Furthermore, the code constellation has a lower error rate deterioration.
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公开(公告)号：EP0039150A3
公开(公告)日：1982-07-21
申请号：EP81301505
申请日：1981-04-07
Applicant: SONY CORPORATION
Inventor： Wilkinson, James Hedley
CPC classification number: H04L7/048
Abstract: Frame information is recovered from a stream of binary data formed at a transmitter (1) from a block of m xn information bits comprising m groups of n bits plus m parity bits, one for each said group of n bits, these parity bits having then been scrambled by performing an exclusive-OR operation in a gate (5) on each parity bit with a respective bit of an m-bit parity scrambling code, said block of bits together with the scrambled parity bits forming a frame for transmission over a transmission link (3). At a receiver (2) new parity bits are produced in a parity bit generator (9) at the incoming bit rate from the incoming stream of binary data by forming a new parity bit from each successive moving group of n +1 incoming bits. The new parity bits are cyclically distributed to n + 1 m-bit shift registers (10,11,12,13), and a framing signal is produced when one of the shift registers (10,11,12,13) holdsm bits substantially corresponding to the m bits of the parity scrambling code.
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