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21.发明公开TRANSMISSION DEVICE, RECEPTION DEVICE, AND TRANSMISSION/RECEPTION SYSTEM 审中-公开SENDEVORRICHTUNG，EMPFANGSVORRICHTUNG UND SENDE- / EMPFANGSSYSTEM
公开(公告)号：EP3133823A1
公开(公告)日：2017-02-22
申请号：EP15779958.6
申请日：2015-03-11
发明人： TAKEUCHI, Ryo , MIURA, Satoshi
IPC分类号： H04N21/436 , H04L7/08
CPC分类号： H04L7/08 , G09G5/006 , G09G5/18 , G09G2340/02 , G09G2370/04 , G09G2370/10 , H04N5/04 , H04N21/23602 , H04N21/4342 , H04N21/436
摘要： A transmission/reception system 1 includes a transmission device 10 configured to transmit image data and a reception device 20 configured to receive the image data transmitted from the transmission device 10. The transmission device 10 includes a serializer 11, an encoding unit 12, a data buffering unit 13, a data selection unit 14, a counter 15, and a synchronization signal generation unit 16. The data buffering unit 13 buffers data every n bits in synchronization with the clock. The data selection unit 14 outputs m-bit data selected from the data buffered by the data buffering unit 13 on the basis of a count value from the counter 15.
摘要翻译： 发送/接收系统1包括被配置为发送图像数据的发送设备10和被配置为接收从发送设备10发送的图像数据的接收设备20.发送设备10包括串行器11，编码单元12，数据 缓冲单元13，数据选择单元14，计数器15和同步信号生成单元16.数据缓冲单元13与时钟同步地每n位缓冲数据。 数据选择单元14基于来自计数器15的计数值输出从数据缓冲单元13缓冲的数据中选择的m位数据。
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公开(公告)号：EP2075949B1
公开(公告)日：2014-11-05
申请号：EP07806838.4
申请日：2007-09-06
发明人： OZAWA, Seiichi
CPC分类号： H04L7/033 , H03L7/091 , H04L7/0083 , H04L7/0087 , H04L25/03057
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公开(公告)号：EP2521269A4
公开(公告)日：2013-11-13
申请号：EP10840926
申请日：2010-12-22
发明人： NEZUKA TOMOHIRO
CPC分类号： H03M3/464
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公开(公告)号：EP2166695A4
公开(公告)日：2012-10-10
申请号：EP08711035
申请日：2008-02-08
发明人： OMOTE KAZUYUKI , SAITO RYUTARO
CPC分类号： H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0337
摘要： In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.
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公开(公告)号：EP2458773A1
公开(公告)日：2012-05-30
申请号：EP10802201.3
申请日：2010-07-14
发明人： OZAWA Seiichi , YAMAMOTO Shuhei
CPC分类号： H04L7/033 , H03L7/0891
摘要： A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value δ to or from a variable Δ when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable Δ when the value of the variable Δ is equal to or more than +N or when the value of the variable Δ is equal to or less than -N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14). The potential adjustment portion (16) increases or decreases a potential at a first end of a capacitive element (15) based on the signals (UP) and (DN).
摘要翻译： 时钟数据恢复装置（1A）包括取样器部分（11），相位比较部分（12），驱动部分（13），电荷泵（14），电容元件（15），电位调节部分 16）和压控振荡器（17）。 当相位相对于输入数字信号延迟时钟（CKX）的相位时，相位比较部分（12）输出成为有效值的信号（UP），并输出当 阶段进展。 当信号（UP）和（DN）变为有效值时，驱动部分（13）增加或减少值“或从变量”增加或减少值“，当值” 变量“等于或大于+ N或当变量的值”等于或小于-N时，信号（UPFRQ）和（DNFRQ）被输出到电荷泵14。 电位调整部（16）基于信号（UP）和（DN）增大或减小电容元件（15）的第一端的电位。
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公开(公告)号：EP2075949A4
公开(公告)日：2010-12-29
申请号：EP07806838
申请日：2007-09-06
发明人： OZAWA SEIICHI
CPC分类号： H04L7/033 , H03L7/091 , H04L7/0083 , H04L7/0087 , H04L25/03057
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27.发明公开TRANSMITTER APPARATUS, RECEIVER APPARATUS AND COMMUNICATION SYSTEM 有权SENDEVORRICHTUNG，EMPFANGSVORRICHTUNG UND KOMMUNIKATIONSSYSTEM
公开(公告)号：EP2211524A1
公开(公告)日：2010-07-28
申请号：EP09824721.6
申请日：2009-10-27
摘要： Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal S data that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal S data in the transmission device 2 is changed. The receiving device 3 that received the serial data signal S data receives training data T data from the transmission device 2 when it is determined that the serial data signal S data is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.
摘要翻译： 提供具有简单配置并能够可靠地执行改变的比特率的确认的发送设备，接收设备和通信系统。 通信系统1将串行数据信号S data的比特率当时钟的周期的常数倍的周期设定为恒定值的串行数据信号S data发送给接收装置3 变速装置2变更。 接收到串行数据信号S data的接收装置3当确定串行数据信号S data是时钟周期的恒定倍数的周期的恒定值时，从发送装置2接收训练数据T数据 并进行确认改变的比特率的处理。
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公开(公告)号：EP2079210A1
公开(公告)日：2009-07-15
申请号：EP07806841.8
申请日：2007-09-06
发明人： OZAWA, Seiichi
摘要： A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n-1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n-1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.
摘要翻译： 时钟/数据恢复装置1包括采样器10，检测器20，偏移确定部分30，时钟输出部分40和DA转换器50.时钟信号CK和CKX的相位被调整以便与 输入数字信号的相位。 在采样器10中添加的偏移量（±Voff）被调整为与值D（n-1）为高电平的情况下的第一信号的数据转换时间分布的峰值时间相匹配，并且是 调整为在值D（n-1）为低电平的情况下与第二信号的数据转换时间分布的峰值时间相匹配。 输出时钟信号CK和CKX中的任一个作为恢复的时钟信号。 输出数字值D（n）的时间序列数据作为恢复数据。
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公开(公告)号：EP1956747A1
公开(公告)日：2008-08-13
申请号：EP06832774.1
申请日：2006-11-16
发明人： OZAWA, Seiichi
IPC分类号： H04L7/033
CPC分类号： H04L7/033 , H04L7/0025 , H04L7/0087
摘要： With the clock data restoration device 1, as a result of the processing of a loop which comprises the sampler section 10, detection section 20, timing determination section 30, and clock output section 40, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n-2) and value D(n-1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n-2) and value D(n-1) of the preceding two bits are equal to one another.
摘要翻译： 利用时钟数据恢复装置1，由于包括采样器部分10，检测部分20，定时确定部分30和时钟输出部分40的循环处理的结果，时钟信号CKXA的各个相位，时钟信号 CKXB和时钟信号CK被调整以与输入数字信号的相位相匹配，调整由时钟信号CKXA指示的数字信号采样时间以匹配数据转换时间分布的峰值时间，其中值D （n-2）和前两位的值D（n-1）彼此不同，并且调整由时钟信号CKXB指示的数字信号采样时间，以匹配数据转换时间分布的峰值时间 前两位的值D（n-2）和值D（n-1）彼此相等的情况。
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公开(公告)号：EP3316523A1
公开(公告)日：2018-05-02
申请号：EP15896360.3
申请日：2015-06-25
发明人： FUJIKI, Rei , TAKEUCHI, Ryo , MURAKAMI, Takayuki
IPC分类号： H04L12/40
CPC分类号： G06F13/4291 , G06F2213/0016 , H04B10/40 , H04L12/40
摘要： A first communication unit 21 of a host-side transceiver device 20 performs communication based on an I 2 C communication scheme with a host device 10 and receives an access request signal sent from the host device 10. A second communication unit 22 performs communication based on a communication scheme different from the I 2 C communication scheme with a remote-side transceiver device 30 and sends the access request signal received by the first communication unit 21 to the remote-side transceiver device 30. The first communication unit 21 notifies the host device 10 that the first communication unit 21 has received the access request signal sent from the host device 10 before the access to the remote device 40 based on the access request signal sent from the second communication unit 22 ends.
摘要翻译： 主机侧收发器装置20的第一通信单元21基于与主机装置10的I2C通信方案执行通信，并且接收从主机装置10发送的访问请求信号。第二通信单元22基于通信 方案不同于与远程侧收发器装置30的I2C通信方案，并且将由第一通信单元21接收的访问请求信号发送到远程侧收发器装置30.第一通信单元21通知主机装置10第一 通信单元21在基于从第二通信单元22发送的访问请求信号结束对远程装置40的访问之前接收到从主机装置10发送的访问请求信号。
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