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21.发明公开Process for fabricating an ASIC device having a gate-array function block 失效一种制备具有一个门阵列功能块中的专用集成电路（ASIC）的过程。
公开(公告)号：EP0609047A3
公开(公告)日：1996-02-28
申请号：EP94300533.0
申请日：1994-01-25
申请人： HITACHI, LTD.
发明人： Fukuda, Hideki , Hagiwara, Yoshimune , Ito, Satoru , Torii, Shuichi , Kozawa, Tokinori , Yamashiro, Osamu
CPC分类号： H01L27/0207 , H01L21/82
摘要： An IC device to be newly developed has at least one first function block (11A-11C, 12A, 12B, 14) and at least one second function block (13A, 13B) in which the first and second function blocks of the to-be-newly developed IC device is formed in a single semiconductor substrate, and logic design data of the first function block is available and that of the second function block needs to be newly prepared at a start of fabrication of the IC device. The IC device is, in one embodiment of the present invention, fabricated by starting logic design (53) of the second function block to prepare logic design data of the second function block while doped layers are formed (55) in a semiconductor substrate for the first and second function blocks to provide a semi-completed IC chip, performing (57) mask design of wiring conductor pattern using the logic design data of the first function block and later obtained logic design data of said second function block to prepare mask design data for the IC device, and forming (57) conductor pattern using the mask design data on the semi-completed IC chip to complete a newly developed IC device.
摘要翻译： 将被新开发的IC装置具有至少一个第一功能块（11A-11C，12A，12B，14）和至少一个第二功能块（13A，13B），其中的所述待与第一和第二功能块 -newly开发IC装置被形成在一个单一的半导体衬底，并在第一功能块的逻辑设计数据是可用的，也做了第二功能块的需要在IC器件的制造的开始被重新制备。 的IC器件是，在本发明的一个方式，通过启动第二功能块，以制备第二功能块的逻辑设计数据的逻辑设计（53），而掺杂层形成（55）在半导体的衬底上制造 第一和第二功能块以提供一个半完成的IC芯片，使用所述第一功能块的逻辑设计数据和所述第二功能块的后面获得逻辑设计数据（57）的布线导体图案的掩模设计，制备掩模设计数据执行 对于使用半完成的IC芯片上的掩模设计数据来完成一个新开发的IC器件的IC器件，以及形成（57）的导体图案。
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22.发明授权Processor capable of executing one or more programs by a plurality of operation units 失效能够由多个操作单位执行一个或多个程序的处理人员
公开(公告)号：EP0180227B1
公开(公告)日：1993-03-24
申请号：EP85113878.4
申请日：1985-10-31
申请人： HITACHI, LTD.
IPC分类号： G06F9/28
CPC分类号： G06F9/28 , G06F9/3885
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公开(公告)号：EP0361525A3
公开(公告)日：1991-03-13
申请号：EP89118106.7
申请日：1989-09-29
申请人： HITACHI, LTD.
发明人： Sawase, Terumi , Hagiwara, Yoshimune , Nakamura, Hideo , Hatori, Hiroyuki , Baba, Shirou , Akao, Yasushi
IPC分类号： G06F15/78
CPC分类号： G06F9/3879 , G06F9/24 , G06F9/3897 , G06F11/2236 , G06F15/7814 , G06F15/7867
摘要： A single chip microcomputer comprises a control circuit (12a, 12b), a processing circuit (13a, 13b) and a plurality of address register - status register pairs. A logical unit formed within the control circuit (12a, 12b) comprises an electrically writable non-volatile semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the plurality of address register - status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.
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24.发明授权A pulse width modulation circuit and an analog product forming integration circuit using such modulation circuit 失效脉冲宽度调制电路和使用这种调制电路形成集成电路的模拟产品
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公开(公告)号：EP0182963A2
公开(公告)日：1986-06-04
申请号：EP85107059.9
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： In a digital signal processor comprising interface means for data input output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.
摘要翻译： 一种数字信号处理器，包括用于与外部设备进行数据输入/输出的接口装置; 数据总线（21,22）; 数据存储器（5,6）; 浮点乘数（14），用于添加指数部分和乘以一对数据的尾数部分; 浮动加法器/减法器（15）; 蓄能器（16）; 开关电路（17）和控制电路（4），所述浮动加法器/减法器包括用于调整两个浮点数据的调整装置（67至69,63至65） 加法器（75），用于将两个浮点数据的两个经调整的尾数部分相加; 用于从加法器移位输出数据的左移位电路（76） 零检测器（79），用于提供第一移位数据信号; 校正电路（85）和控制电路（89），用于产生下溢信号并提供两个数据之和的归一化指数部分; 用于向移位电路提供第二移位数据信号的恒定加法器电路（77）和选择器（81），或根据是否产生下溢信号的第一移位数据信号。
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公开(公告)号：EP0051422A3
公开(公告)日：1982-12-01
申请号：EP81305062
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： A digital signal processor comprising interface means for data inputoutput with an external device; a first data bus (21) which has a predetermined number of bits and which is connected to the interface means; data memories (5, 6) connected to the data bus; a second data bus (22) onto which a data from the data memories is read out; a floating point multiplier (14) connected with the first and second data buses and for adding exponent parts and multiplying mantissa parts of a pair of data applied, to deliver an operated result having a number of bits larger than that of the first data bus; a floating adder-subtracter (15) including an input selection portion selecting a pair of data appointed by a program instruction from amongst a plurality of data containing the output of the multiplier, and for adding subtracting said pair of data; an accumulator (16) for holding a data delivered from the adder subtracter and having a number of bits larger than that of the first data bus; a third data bus (27) which has a number of bits larger than that of the first data bus and which supplies an output of said accumulator to said input selection portion of said adder subtracter; a switching circuit (17) connected between said accumulator and the first data bus and for reducing the number of bits of the output data of the accumulator and then supplying the resultant data to the first data bus; and a control circuit (4) for controlling the operations of the respective means in accordance with program instructions.
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