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公开(公告)号：EP0182963A3
公开(公告)日：1986-10-01
申请号：EP85107059
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： In a digital signal processor comprising interface means for data input output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.
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公开(公告)号：EP0182963A2
公开(公告)日：1986-06-04
申请号：EP85107059.9
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： In a digital signal processor comprising interface means for data input output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.
摘要翻译： 一种数字信号处理器，包括用于与外部设备进行数据输入/输出的接口装置; 数据总线（21,22）; 数据存储器（5,6）; 浮点乘数（14），用于添加指数部分和乘以一对数据的尾数部分; 浮动加法器/减法器（15）; 蓄能器（16）; 开关电路（17）和控制电路（4），所述浮动加法器/减法器包括用于调整两个浮点数据的调整装置（67至69,63至65） 加法器（75），用于将两个浮点数据的两个经调整的尾数部分相加; 用于从加法器移位输出数据的左移位电路（76） 零检测器（79），用于提供第一移位数据信号; 校正电路（85）和控制电路（89），用于产生下溢信号并提供两个数据之和的归一化指数部分; 用于向移位电路提供第二移位数据信号的恒定加法器电路（77）和选择器（81），或根据是否产生下溢信号的第一移位数据信号。
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公开(公告)号：EP0051422A3
公开(公告)日：1982-12-01
申请号：EP81305062
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： A digital signal processor comprising interface means for data inputoutput with an external device; a first data bus (21) which has a predetermined number of bits and which is connected to the interface means; data memories (5, 6) connected to the data bus; a second data bus (22) onto which a data from the data memories is read out; a floating point multiplier (14) connected with the first and second data buses and for adding exponent parts and multiplying mantissa parts of a pair of data applied, to deliver an operated result having a number of bits larger than that of the first data bus; a floating adder-subtracter (15) including an input selection portion selecting a pair of data appointed by a program instruction from amongst a plurality of data containing the output of the multiplier, and for adding subtracting said pair of data; an accumulator (16) for holding a data delivered from the adder subtracter and having a number of bits larger than that of the first data bus; a third data bus (27) which has a number of bits larger than that of the first data bus and which supplies an output of said accumulator to said input selection portion of said adder subtracter; a switching circuit (17) connected between said accumulator and the first data bus and for reducing the number of bits of the output data of the accumulator and then supplying the resultant data to the first data bus; and a control circuit (4) for controlling the operations of the respective means in accordance with program instructions.
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公开(公告)号：EP0182963B1
公开(公告)日：1991-01-02
申请号：EP85107059.9
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
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公开(公告)号：EP0051422B1
公开(公告)日：1988-06-15
申请号：EP81305062.2
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
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公开(公告)号：EP0051422A2
公开(公告)日：1982-05-12
申请号：EP81305062.2
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： A digital signal processor comprising interface means for data inputoutput with an external device; a first data bus (21) which has a predetermined number of bits and which is connected to the interface means; data memories (5, 6) connected to the data bus; a second data bus (22) onto which a data from the data memories is read out; a floating point multiplier (14) connected with the first and second data buses and for adding exponent parts and multiplying mantissa parts of a pair of data applied, to deliver an operated result having a number of bits larger than that of the first data bus; a floating adder-subtracter (15) including an input selection portion selecting a pair of data appointed by a program instruction from amongst a plurality of data containing the output of the multiplier, and for adding subtracting said pair of data; an accumulator (16) for holding a data delivered from the adder subtracter and having a number of bits larger than that of the first data bus; a third data bus (27) which has a number of bits larger than that of the first data bus and which supplies an output of said accumulator to said input selection portion of said adder subtracter; a switching circuit (17) connected between said accumulator and the first data bus and for reducing the number of bits of the output data of the accumulator and then supplying the resultant data to the first data bus; and a control circuit (4) for controlling the operations of the respective means in accordance with program instructions.
摘要翻译： 一种数字信号处理器，包括用于使用外部设备输出数据的接口装置; 第一数据总线（21），其具有预定数量的位，并且连接到所述接口装置; 连接到数据总线的数据存储器（5,6）; 读出来自数据存储器的数据的第二数据总线（22）; 一个与第一和第二数据总线连接的浮点乘法器（14），并且用于增加指令部分和乘以所应用的一对数据的尾数部分，以传送比第一数据总线的位数大的位数的操作结果; 浮动加法器减法器（15），包括：输入选择部分，从包含所述乘法器的输出的多个数据中选择由程序指令指定的一对数据，并且用于加减去所述数据对; 累加器（16），用于保存从所述加法器减法器传送的数据，并且具有大于所述第一数据总线的位数; 第三数据总线（27），其具有比所述第一数据总线的位数大的位数，并且将所述累加器的输出提供给所述加法器减法器的所述输入选择部分; 连接在所述累加器与所述第一数据总线之间的切换电路（17），用于减少所述累加器的输出数据的位数，然后将所得数据提供给所述第一数据总线; 以及用于根据程序指令控制各个装置的操作的控制电路（4）。
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