公开(公告)号：EP2656347A2

公开(公告)日：2013-10-30

申请号：EP11851426.4

申请日：2011-12-16

申请人： Intel Corporation

发明人： NALE, Bill

IPC分类号： G11C7/10 ,  G06F13/14 ,  G06F12/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/109 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/105

摘要： In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

公开(公告)号：EP4273705A1

公开(公告)日：2023-11-08

申请号：EP23167111.6

申请日：2023-04-06

申请人： INTEL Corporation

发明人： BAINS, Kuljit S. ,  LEE, Jongwon ,  LEVY, Tomer ,  NALE, Bill ,  RADJAI, Amir Ali

IPC分类号： G06F13/16 ,  G11C7/10 ,  G11C11/406

摘要： Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.

公开(公告)号：EP3327578B1

公开(公告)日：2020-06-03

申请号：EP18151893.7

申请日：2015-11-18

申请人： Intel Corporation

发明人： MORRIS, Brian ,  NALE, Bill ,  BLANKENSHIP, Robert ,  SWANSON, Jeffrey

IPC分类号： G06F13/16

公开(公告)号：EP3453022A1

公开(公告)日：2019-03-13

申请号：EP17793191.2

申请日：2017-05-02

申请人： INTEL Corporation

发明人： BAINS, Kuljit ,  NALE, Bill ,  AGARWAL, Rajat

IPC分类号： G11C29/42 ,  G06F11/10 ,  G11C11/409

公开(公告)号：EP3035199B1

公开(公告)日：2018-06-27

申请号：EP15195264.5

申请日：2015-11-18

申请人： Intel Corporation

发明人： MORRIS, Brian S. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  SWANSON, Jeffrey C.

IPC分类号： G06F13/38 ,  G06F13/16

CPC分类号： G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

摘要： A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：EP3238078A1

公开(公告)日：2017-11-01

申请号：EP15874050.6

申请日：2015-11-26

申请人： Intel Corporation

发明人： MORRIS, Brian, S. ,  NALE, Bill ,  BLANKENSHIP, Robert, G. ,  LIU, Yen-Cheng

IPC分类号： G06F13/16 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026

摘要： A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

摘要翻译： 通过缓冲存储器访问链路从主机设备接收推测读取请求以获取与特定地址相关联的数据。 将读取请求发送到存储设备。 响应于读取请求从存储器装置接收数据，并且将接收到的数据作为对在推测性读取请求之后接收到的请求读取请求的响应发送到主机装置。

公开(公告)号：EP3234778A1

公开(公告)日：2017-10-25

申请号：EP15870614.3

申请日：2015-11-23

申请人： INTEL Corporation

发明人： MORRIS, Brian S. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  HENDRICKSON, Eric L.

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F13/16 ,  G06F13/42 ,  G06F12/08

CPC分类号： G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

摘要： Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

摘要翻译： 数据通过链路从内存缓冲设备发送到主机设备。 数据中的错误被确定。 读取响应取消信号被发送到主机设备以向主机设备指示错误，其中读取响应取消信号将在数据被从存储器缓冲设备发送到主机设备之后发送。

公开(公告)号：EP3035199A1

公开(公告)日：2016-06-22

申请号：EP15195264.5

申请日：2015-11-18

申请人： Intel Corporation

发明人： MORRIS, Brian S. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  SWANSON, Jeffrey C.

IPC分类号： G06F13/38 ,  G06F13/16

CPC分类号： G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

摘要： A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

摘要翻译： 读取返回序列将通过事务缓冲存储器接口发送到主机设备，其中该序列至少包括第一读取返回到第一读取请求和第二读取返回到第二读取请求。 第二读取返回的跟踪器标识符被编码在第一读取返回中，并且第一读取返回与第二读取返回的跟踪器标识符一起发送到主机设备。 在发送第一个读取返回后，第二个读取返回被发送到主机设备。