公开(公告)号：EP3901952A1

公开(公告)日：2021-10-27

申请号：EP21177402.1

申请日：2017-10-30

申请人： Intel Corporation

发明人： COX, Christopher E. ,  BAINS, Kuljit ,  MOZAK, Christopher P. ,  MCCALL, James A. ,  VASANTH, Akshith ,  NALE, Bill

IPC分类号： G11C11/406 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4093

摘要： A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：EP3423945A1

公开(公告)日：2019-01-09

申请号：EP17763682.6

申请日：2017-01-16

申请人： Intel Corporation

发明人： VERGIS, George ,  BAINS, Kuljit S. ,  NALE, Bill

IPC分类号： G06F12/02

公开(公告)号：EP3370156A1

公开(公告)日：2018-09-05

申请号：EP18165254.6

申请日：2015-11-26

申请人： Intel Corporation

发明人： MORRIS, Brian S. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  LIU, Yen-Cheng

IPC分类号： G06F12/0884 ,  G06F12/0862 ,  G06F12/0831

CPC分类号： G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026 ,  Y02D10/13

摘要： An apparatus comprising a translational memory buffer (TMXB) device comprising a receiver to receive a speculative read request from a host controller over an interface, wherein the speculative memory read request identifies a particular address in a memory, and the interface uses a physical layer and a link layer of another interconnect protocol, a scheduler, and a memory controller to obtain data from the particular address based on the speculative read request, store the data in a buffer, identify a demand read from the host controller corresponding to the speculative read request and generate a read return comprising the data, wherein the read return is to be sent to the host controller over the interface in response to the demand read.

公开(公告)号：EP3364304A1

公开(公告)日：2018-08-22

申请号：EP18165222.3

申请日：2011-09-30

申请人： INTEL Corporation

发明人： NALE, Bill ,  RAMANUJAN, Raj K. ,  SWAMINATHAN, Muthukumar P. ,  THOMAS, Tessil ,  POLEPEDDI, Taarinya

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F11/10 ,  G06F13/14 ,  G06F13/16 ,  G06F9/46 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0811

CPC分类号： G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：EP3238079A1

公开(公告)日：2017-11-01

申请号：EP15874051.4

申请日：2015-11-27

申请人： Intel Corporation

发明人： MORRIS, Brian S. ,  SWANSON, Jeffrey C. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  WILLEY, Jeff ,  HENDRICKSON, Eric L.

IPC分类号： G06F13/16 ,  G06F12/08

CPC分类号： G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

摘要： A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

摘要翻译： 识别对应于来自通过缓冲存储器接口接收的来自主机设备的多个写入请求的对存储器的多个完成的写入。 完成包被发送到包括多个写入完成的主机设备以对应于多个完成的写入。

公开(公告)号：EP4235439A1

公开(公告)日：2023-08-30

申请号：EP23170683.9

申请日：2017-01-16

申请人： INTEL Corporation

发明人： VERGIS, George ,  BAINS, Kuljit S. ,  NALE, Bill

IPC分类号： G06F12/02 ,  G11C5/04 ,  G11C5/06 ,  H01L23/00 ,  G06F13/42 ,  G11C7/10

摘要： Examples include techniques to invert a command/address or interpret command/address logic as inverted at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and interpret the command/address logic indicated in the command/address signal as inverted or not based on a strap pin of the memory device.

公开(公告)号：EP4109270A1

公开(公告)日：2022-12-28

申请号：EP22161815.0

申请日：2022-03-14

申请人： INTEL Corporation

发明人： MAKARAM, Raghunandan ,  YAP, Kirk S. ,  AGARWAL, Rajat ,  VERGIS, George ,  NALE, Bill ,  DOWECK, Jacob

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F21/60 ,  G06F21/79 ,  G11C29/04 ,  G11C7/10 ,  H04L9/06 ,  H04L9/32 ,  G11C7/24

摘要： A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.

公开(公告)号：EP2656347B1

公开(公告)日：2020-02-12

申请号：EP11851426.4

申请日：2011-12-16

申请人： Intel Corporation

发明人： NALE, Bill

IPC分类号： G11C7/10 ,  G06F13/14 ,  G06F12/00

公开(公告)号：EP3533058A1

公开(公告)日：2019-09-04

申请号：EP17864379.7

申请日：2017-10-30

申请人： Intel Corporation

发明人： COX, Christopher E. ,  BAINS, Kuljit ,  MOZAK, Christopher P. ,  MCCALL, James A. ,  VASANTH, Akshith ,  NALE, Bill

IPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C7/10

公开(公告)号：EP3373146A1

公开(公告)日：2018-09-12

申请号：EP18165252.0

申请日：2015-11-23

申请人： INTEL Corporation

发明人： MORRIS, Brian S. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  HENDRICKSON, Eric L.

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F13/16 ,  G06F13/42 ,  G06F12/08 ,  H04L1/00 ,  H04L1/18

CPC分类号： G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

摘要： An apparatus comprises a buffer chip comprising a memory controller to interface with a memory and convert memory requests into a memory specific protocol corresponding to the memory, a receiver to receive a particular memory request from a processor device over a transactional memory link, a transmitter to send a read return to the processor device, the read return comprising a plurality of packets, wherein the plurality of packets comprises an initial headered packet followed by a headerless packet, the headered packet comprises a header flit and a first number of data flits, the headerless packet comprises a second number of data flits, the second number is less than the first number, the header flit comprises a request transaction identifier (TID) corresponding to data in the first number of data flits, each of the first number of data flits comprises a TID corresponding to data in the second number of data flits, and each of the second number of data flits comprises a TID for data in a subsequent headerless packet.