公开(公告)号：EP3274857A1

公开(公告)日：2018-01-31

申请号：EP16769240.9

申请日：2016-02-22

申请人： Intel Corporation

发明人： WAGH, Mahesh ,  WU, Zuoguo ,  IYER, Venkatraman ,  PASDAST, Gerald S. ,  BIRRITTELLA, Mark S. ,  AGARWAL, Ishwar ,  TEH, Lip Khoon ,  LIM, Su Wei ,  UPADHYAY, Anoop Kumar

IPC分类号： G06F13/42 ,  G06F13/14 ,  H04L12/701

CPC分类号： G06F13/4022 ,  G06F13/36 ,  G06F13/4068

摘要： A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

公开(公告)号：EP3191969A1

公开(公告)日：2017-07-19

申请号：EP14901804.6

申请日：2014-12-24

申请人： Intel Corporation

发明人： PETHE, Akshay ,  WAGH, Mahesh ,  HARRIMAN, David ,  LIM, Su Wei ,  DAS SHARMA, Debendra ,  FROELICH, Daniel ,  IYER, Venkatraman ,  JAUSSI, James ,  WU, Zuoguo

IPC分类号： G06F13/14

CPC分类号： G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

摘要： Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.

摘要翻译： 这里描述了用于嵌入式高速串行接口方法的技术。 该技术包括用于边带信令的装置，该装置包括第一串行边带链路模块和第二串行边带链路模块。 第一串行边带链路模块是经由第一信令通道将分组从上游端口传播到下游端口，并且第二串行边带链路模块是经由第二信令通道将分组从下游端口传播到上游端口。

公开(公告)号：EP2962210A1

公开(公告)日：2016-01-06

申请号：EP13876632.4

申请日：2013-02-28

申请人： Intel Corporation

发明人： WAGH, Mahesh

IPC分类号： G06F13/14 ,  G06F13/42

CPC分类号： G06F13/42 ,  G06F3/0661 ,  G06F13/387 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

摘要： An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.

摘要翻译： 一个方面的互连体系结构设备包括用于生成与LLI不同的互连协议的事务的处理器。 互连体系结构设备还包括与处理器耦合的转换逻辑。 转换逻辑是将与LLI不同的互连协议的事务转换为LLI包。 互连架构设备还包括与转换逻辑耦合的LLI控制器。 LLI控制器将互连体系结构设备与LLI链接耦合。 LLI控制器将在LLI链路上传输LLI数据包。

公开(公告)号：EP2867783A1

公开(公告)日：2015-05-06

申请号：EP13810571.3

申请日：2013-06-26

申请人： Intel Corporation

发明人： WAGH, Mahesh

IPC分类号： G06F13/14 ,  G06F13/42

CPC分类号： G06F1/3253 ,  G06F1/3209 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151

摘要： Methods and apparatus for provision of a low power, low frequency squelch break protocol are described. In some embodiments, a fixed or variable time transmitter LFPS (Low Frequency Periodic Signaling) mechanism may be used that does not require a handshake and therefore much simpler in implementation than USB3 (Universal Serial Bus 3.0), for example. Also, an embodiment does not require a link common mode to be established and therefore may be optimized to support shorter durations for effecting exit from an electrical idle state that may be established via power-gating, for example. Other embodiments are also disclosed.

公开(公告)号：EP3879410A1

公开(公告)日：2021-09-15

申请号：EP21168844.5

申请日：2017-06-14

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  MYERS, Mark S. ,  VAN DOREN, Stephen R. ,  ZIAKAS, Dimitrios ,  COURY, Bassam

IPC分类号： G06F13/38

摘要： The present disclosure provides an apparatus comprising a plurality of processing cores integrated onto multiple integrated circuit dies in a package, the plurality of processing cores to execute instructions and process data, memory logic to couple to a memory device, a coherent interconnect fabric to connect the plurality of processing cores and the memory logic and a physical, PHY, layer interface. The physical, PHY, layer interface comprising a plurality of connectors coupled to a plurality of data lanes, the plurality of connectors including a first subset of the connectors to communicate in accordance with a first interconnect protocol, a second subset of the connectors to communicate in accordance with a second interconnect protocol, and a third subset of the connectors to communicate in accordance with a third interconnect protocol. The apparatus comprising a first logical sub-block to encode data in accordance with the first interconnect protocol, a second logical sub-block to encode data in accordance with the second interconnect protocol and a third logical sub-block to encode data in accordance with the third interconnect protocol and a multiplexer. The multiplexer is to connect the first subset of connectors to the first logical sub-block, to connect the second subset of the connectors to the second logical sub-block, and to connect the third subset of the connectors to the third logical sub-block. The apparatus comprising a first transaction layer to communicate data between the coherent interconnect fabric and the first logical sub-block in accordance with the first interconnect protocol; a second transaction layer to communicate data between the coherent interconnect fabric and the second logical sub-block in accordance with the second interconnect protocol; and a third transaction layer to communicate data between the coherent interconnect fabric and the third logical sub-block in accordance with the third interconnect protocol.

公开(公告)号：EP3846042A1

公开(公告)日：2021-07-07

申请号：EP20206632.0

申请日：2016-02-22

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  WU, Zuoguo ,  IYER, Venkatraman ,  PASDAST, Gerald S. ,  BIRRITTELLA, Mark S. ,  AGARWAL, Ishwar ,  TEH, Lip Khoon ,  LIM, Su Wei ,  UPADHYAY, Anoop Kumar

IPC分类号： G06F13/42 ,  G06F13/14 ,  H04L12/701 ,  G06F13/36 ,  G06F13/40

摘要： The present disclosure provides an integrated circuit die. The integrated circuit die comprising a hard IP (HIP) subassembly comprising a plurality of hard logic blocks, a hard logic block associated with a plurality of data lanes. The plurality of data lanes having separate per-lane enables. The integrated circuit die comprising a plurality of protocol-specific logic blocks to communicate data in accordance with a corresponding plurality of data communication protocols. The plurality of protocol-specific logic blocks including a first protocol-specific logic block to communicate data in accordance with a first data communication protocol and a second protocol-specific logic block to communicate data in accordance with a second data communication protocol. The integrated circuit die comprising a soft IP (SIP) assembly having at least one soft logic block comprising routable logic to selectively map a data lane of the plurality of data lanes to the first protocol-specific logic block and a data lane of the plurality of data lanes to the second protocol-specific logic block.

公开(公告)号：EP3796181A1

公开(公告)日：2021-03-24

申请号：EP20206623.9

申请日：2016-02-22

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  WU, Zuoguo ,  IYER, Venkatraman ,  PASDAST, Gerald S. ,  BIRRITTELLA, Mark S. ,  AGARWAL, Ishwar ,  TEH, Lip Khoon ,  LIM, Su Wei ,  UPADHYAY, Anoop Kumar

IPC分类号： G06F13/42 ,  G06F13/14 ,  H04L12/701 ,  G06F13/36 ,  G06F13/40

摘要： The present disclosure provides a multi-chip package comprising a substrate, a first integrated circuit (IC) die packaged onto the substrate and a second IC die packaged onto the substrate and connected to the first IC die using a multi-chip package link (MCPL). The MCPL including an upstream channel and a downstream channel each associated with a set of lanes. The first IC die comprising a CPU and an interface to connect the CPU. The interface including a physical layer (PHY) to provide a physical connection over which data is communicated between the first IC die and the second IC die. The PHY comprising a transmitter to transmit data to the second IC die, a receiver to receive data from the second IC die and a clock recovery circuit to center a clock signal in both the time domain and the voltage domain and to receive a clock signal from the second IC die over a strobe lane. To center in the time domain, the clock recovery circuit is to determine a phase of the clock signal and to adjust the phase of the clock signal. To center in the voltage domain, the clock recovery circuit is to adjust a reference voltage. The clock recovery circuit to sample data signals in accordance with the reference voltage and the clock signal using a plurality of data samplers for each lane.

公开(公告)号：EP3719660A1

公开(公告)日：2020-10-07

申请号：EP20156893.8

申请日：2020-02-12

申请人： INTEL Corporation

发明人： HOR, Joon Teik ,  SONG, Ting Lok ,  WAGH, Mahesh ,  LIM, Su Wei

IPC分类号： G06F13/42 ,  G06F13/38

摘要： Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：EP3063640B1

公开(公告)日：2020-10-07

申请号：EP13896809.4

申请日：2013-10-30

申请人： Intel Corporation

发明人： HARRIMAN, David J. ,  WAGH, Mahesh ,  ISMAIL, Abdul R. ,  FROELICH, Daniel S.

IPC分类号： G06F13/00 ,  G06F1/04 ,  H04L12/26

公开(公告)号：EP3087491B1

公开(公告)日：2018-12-05

申请号：EP13900085.5

申请日：2013-12-26

申请人： Intel Corporation

发明人： WU, Zuoguo J. ,  WAGH, Mahesh ,  DAS SHARMA, Debendra ,  PASDAST, Gerald S. ,  AYYASAMY, Ananthan ,  LI, Xiaobei ,  BLANKENSHIP, Robert G. ,  SAFRANEK, Robert J.

IPC分类号： G06F13/14 ,  G06F13/38

CPC分类号： G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.