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公开(公告)号：EP1141959A1
公开(公告)日：2001-10-10
申请号：EP00904822.4
申请日：2000-01-03
CPC分类号： G11C7/06 , G11C7/1048 , G11C11/22
摘要： An integrated memory comprising m > 1 bit lines (BL0..3) that are connected to an input of a read-write amplifier (SA) via a switching element (T1) whereby only one switching element (T1) is conductively connected for each read or write access. The memory is provided with a switching unit (C) that influences read or write access occurring by means of the read-write amplifier (SA) and bit lines (BL0..3), whereby said unit is provided with an activation input. A column-end decoder (DEC) comprises a first decoder stage (A) and m second decoder stages (N). The outputs (LCSL0..3) of the second decoder stages (N) are connected to a control input for each of the switching elements (T1). The output (GCSL0) of the first decoder stage (A) is connected to the activation input of the switching unit (C).
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公开(公告)号：EP1141834A1
公开(公告)日：2001-10-10
申请号：EP99966804.9
申请日：1999-12-01
发明人： HÖNIGSCHMID, Heinz , BRAUN, Georg , MAJDIC, Andrej
IPC分类号： G06F11/20
CPC分类号： G11C29/78 , G11C29/702
摘要： The invention relates to an IC memory with a normal bit line (BL) for transmitting data from or to normal memory cells (MC) connected to said line. The IC memory is further provided with a normal sense amplifier (SA1) which is linked via a line (L1) at the one end with the normal bit line (BL) and at the other end with a data line (DQ1). Said sense amplifier amplifies the data read out from the normal memory cells (MC). The memory also comprises a redundant sense amplifier (RSA1) for replacing the normal sense amplifier (SA1) in the case of a redundancy. Said redundant sense amplifier is also linked at the one end with the line (L1) and at the other end with the data line (DQ1) and amplifies the data read out from the normal memory cells (MC) in the case of a redundancy.
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公开(公告)号：EP1118081A1
公开(公告)日：2001-07-25
申请号：EP99969821.0
申请日：1999-09-13
发明人： RÖHR, Thomas , BÖHM, Thomas , HÖNIGSCHMID, Heinz , BRAUN, Georg
摘要： The invention relates to a memory having writable memory cells (MC) as well as a bit line pair (BL, /BL) which links the memory cells (MC) with a differential read amplifier (SA). A control unit (CTR) serves to precharge the bit lines in several stages before a memory cell (MC) is conductively connected to one of the bit lines (BL) during a read access. During a write access the control unit (CTR) carries out no more than a part of the steps provided for a read access and required for precharging the bit lines, before the read amplifier transmits data to the bit line pair (BL, /BL).
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公开(公告)号：EP1138084B1
公开(公告)日：2005-07-06
申请号：EP99963195.5
申请日：1999-11-03
CPC分类号： H01L29/78391
摘要： A ferroelectric transistor with two source/drain areas (2) and a channel area (3) arranged therebetween in a semiconductor substrate (1). A metal intermediate layer (4) is disposed on the surface of the channel area (3) whereby said intermediate layer forms a Schottky diode with the semiconductor substrate (1) and a ferroelectric layer (5) and a gate electrode (6) are arranged on the surface thereof. The ferroelectric transistor is produced in various steps using silicon process technology.
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25.发明授权FERROELEKTRISCHER SCHREIB-/LESESPEICHER MIT IN REIHE GESCHALTETEN SPEICHERZELLEN (CFRAM) 有权具有串联连接的存储CELL FERRO ELECTRIC读/写存储器（CFRAM）
公开(公告)号：EP1099222B1
公开(公告)日：2003-04-23
申请号：EP99942749.5
申请日：1999-07-01
发明人： SCHNEIDER, Ronny , BRAUN, Georg
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The invention relates to series-connected ferroelectric storage cells with which a resistor or a transistor is connected in series to the ferroelectric capacitor of a respective storage cell. Without impermissibly increasing the access time, the invention provides that the interfering pulses generated by reading out from or writing to the addressed storage cells are reduced at the ferroelectric capacitors of the storage cells which are not directly addressed. Said interfering pulses are reduced in such a way that they virtually no longer influence the storage cells which are not addressed.
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26.发明授权
公开(公告)号：EP1163679B1
公开(公告)日：2002-12-04
申请号：EP00912402.5
申请日：2000-03-02
发明人： BÖHM, Thomas , BRAUN, Georg
IPC分类号： G11C29/00
CPC分类号： G11C29/52
摘要： Before a write and/or read access to one of the memory cells is carried out, a security information stored in a security memory cell is read out. If the security information is characterized by a first logic state an error signal is generated. If the read-out security information is characterized by a second logic state the memory cell is accessed and a write access is carried out to the security memory cell during which a new security information to be he stored having the second logic state is written to the cell.
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公开(公告)号：EP1118081B1
公开(公告)日：2002-12-04
申请号：EP99969821.0
申请日：1999-09-13
发明人： RÖHR, Thomas , BÖHM, Thomas , HÖNIGSCHMID, Heinz , BRAUN, Georg
摘要： The invention relates to a memory having writable memory cells (MC) as well as a bit line pair (BL, /BL) which links the memory cells (MC) with a differential read amplifier (SA). A control unit (CTR) serves to precharge the bit lines in several stages before a memory cell (MC) is conductively connected to one of the bit lines (BL) during a read access. During a write access the control unit (CTR) carries out no more than a part of the steps provided for a read access and required for precharging the bit lines, before the read amplifier transmits data to the bit line pair (BL, /BL).
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公开(公告)号：EP1141835B1
公开(公告)日：2002-07-31
申请号：EP99966834.6
申请日：1999-12-07
发明人： NEUHOLD, Ernst , HÖNIGSCHMID, Heinz , BRAUN, Georg , MANYOKI, Zoltan , BÖHM, Thomas , RÖHR, Thomas
IPC分类号： G06F11/20
CPC分类号： G11C29/808 , G11C29/846
摘要： An integrated memory with two read amplifiers (sAi) and two first redundant read amplifiers (RSA0..3). Said memory also comprises normal bit lines (BL) that merge into at least two individually addressable slots (CL), whereby at least one of said lines is connected to one of the normal read amplifiers from one of said slots. The inventive memory also comprises first redundant bit lines (RBL1) that merge into at least one individually addressable redundant slot (RCL), whereby at least one of said lines is connected to one of the redundant amplifiers (RSA0..3). The first redundant amplifier (RSA0..3) and the redundant slot (RCL) pertaining thereto are provided as replacements for the two normal read amplifiers (Sai) and one of the normal slots (CL).
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公开(公告)号：EP1141959B1
公开(公告)日：2002-07-03
申请号：EP00904822.4
申请日：2000-01-03
CPC分类号： G11C7/06 , G11C7/1048 , G11C11/22
摘要： An integrated memory comprising m > 1 bit lines (BL0..3) that are connected to an input of a read-write amplifier (SA) via a switching element (T1) whereby only one switching element (T1) is conductively connected for each read or write access. The memory is provided with a switching unit (C) that influences read or write access occurring by means of the read-write amplifier (SA) and bit lines (BL0..3), whereby said unit is provided with an activation input. A column-end decoder (DEC) comprises a first decoder stage (A) and m second decoder stages (N). The outputs (LCSL0..3) of the second decoder stages (N) are connected to a control input for each of the switching elements (T1). The output (GCSL0) of the first decoder stage (A) is connected to the activation input of the switching unit (C).
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30.发明公开INTEGRIERTER SPEICHER MIT SPEICHERZELLEN UND REFERENZZELLEN UND ENTSPRECHENDES BETRIEBSVERFAHREN 有权带记忆单元和参考单元及相应的操作方法集成内存
公开(公告)号：EP1163677A1
公开(公告)日：2001-12-19
申请号：EP00918693.3
申请日：2000-03-10
摘要： The integrated memory has two first switching elements (S1) which each connect a bit line (BL0, bBL0) of a first bit line pair to a bit line (BL1, bBL1) of a second bit line pair; and two second switching elements (S2) which each connect one of the reference cells (RC') of one bit line pair (BL0, bBL0) to the bit line (BL1, bBL1) of the other bit line pair that is not connected to the bit line allocated to this reference cell (RC') by the corresponding first switching element. Information is rewritten into the reference cells (RC, RC') through the read amplifier (SAi).
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