公开(公告)号：EP0306712B1

公开(公告)日：1993-12-29

申请号：EP88112792.2

申请日：1988-08-05

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Lu, Nicky Chau-Chun

IPC分类号： G11C7/06 ,  G11C11/409

CPC分类号： G11C11/4091 ,  G11C7/065

公开(公告)号：EP0568818A2

公开(公告)日：1993-11-10

申请号：EP93105501.6

申请日：1993-04-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Bronner, Gary Bela ,  Dhong, Sang Hoo

IPC分类号： G11C11/407 ,  G11C5/14

CPC分类号： G11C5/146

摘要： A semiconductor memory device and operational method having reduced well noise are provided. The memory device includes a plurality of memory cells arranged in rows and columns within an array well and addressable by a plurality of word lines and bit lines. The array well is biased to a desired potential and a sense amplifier is employed to read bit line states during a predefined bit line signal development period. Array well biasing is removed during at least a portion of this signal development, so that the well potential floats (ideally remaining stable) as signals are being developed on the bit lines. This temporary, floating well technique is particularly important for open bit line architectures.

摘要翻译： 提供了具有降低的井噪声的半导体存储器件和操作方法。 存储器件包括多个存储单元，其以阵列阵列内的行和列排列并且可由多个字线和位线寻址。 阵列阱被偏置到期望的电位，并且采用读出放大器来在预定位线信号显影周期期间读取位线状态。 在该信号显影的至少一部分期间去除阵列阱偏置，使得当位线上正在开发信号时，阱电位漂浮（理想地保持稳定）。 这种临时浮动井技术对开放式位线架构尤为重要。

公开(公告)号：EP0550894A1

公开(公告)日：1993-07-14

申请号：EP92122009.1

申请日：1992-12-24

申请人： International Business Machines Corporation

发明人： Bronner, Gary Bela ,  Dhong, Sang Hoo ,  Hwang, Wei ,  Park, Jong Woo ,  Voldman, Steven Howard

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： A high density substrate plate trench DRAM cell memory device and process are described in which a buried region (32) is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate (10). The buried region (32) is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches (22). The buried region (32) is contacted along its perimeter by a reach through region to complete the isolation. The combined regions reduce charge loss due to better control of device parasitics.

摘要翻译： 描述了一种高密度衬底板沟槽DRAM单元存储器件和工艺，其中掩埋区域（32）与深沟槽电容器相邻形成，使得DRAM传输FET的衬底区域可以与半导体衬底上的其他FET电隔离 10）。 掩埋区域（32）通过离子注入和扩散部分地形成以与深沟槽（22）的壁相交。 掩埋区域（32）沿其周边与达到的区域接触以完成隔离。 由于更好地控制器件寄生效应，组合区域减少了电荷损失。

公开(公告)号：EP0540930A2

公开(公告)日：1993-05-12

申请号：EP92117855.4

申请日：1992-10-19

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Hwang, Wei

IPC分类号： H01L27/108 ,  G11C11/409

CPC分类号： H01L27/10805 ,  H01L27/10829 ,  Y10S257/907

摘要： A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts with two different interconnecting layers in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array. In another embodiment, referred to as the side wall bit line structure, the bit lines are constructed by using the conductive side wall spacer rails to connect the interdigitated cells associated to it. By connecting the side wall bit line contacts with two sided-side wall spacer rails in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array.

摘要翻译： 公开了一种用于未来世代高密度半导体存储器设计的新的叉指折叠位线（IFBL）架构。 在架构中，基本交叉点存储单元以行和列正交组织以形成阵列矩阵。 位线在行方向上运行，而字线在列方向上运行。 传输晶体管被设计为与相同的漏极结和相同的位线接触共享，以节省面积。 提供至少两个所描述的实施例的选择。 在一个实施例中，称为偏移位线结构，通过使用两层互连线来连接与之相关联的交叉指示的单元来构造位线。 通过以交替行顺序将位线触点与两个不同的互连层连接起来，真和补补位线将平行于存储器阵列的两侧延伸。 在另一个实施例中，称为侧壁位线结构，通过使用导电侧壁间隔导轨来连接与之相关联的交叉指针的单元来构造位线。 通过以交替的行顺序将侧壁位线触点与双面侧壁间隔轨连接，真和补补位线将平行于存储器阵列的两侧延伸。

公开(公告)号：EP0493659A3

公开(公告)日：1993-03-24

申请号：EP91118320.0

申请日：1991-10-28

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Hwang, Wei ,  Taira, Yoichi

IPC分类号： G11C11/408 ,  G11C8/00

CPC分类号： H03K5/023 ,  G11C11/4085

摘要： A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure (58) having one contact coupled to a wordline (60), a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well (64) about the gate, first and second contacts. An isolating structure (66) is positioned about the N-well (64) to enable it to be a separately controlled from surrounding N-well structures (64). Pulse circuits (52) are coupled to the transistor (58) for applying, when activated, a potential that enables the wordline (60) to transition to a more negative potential. A bias circuit is also provided for biasing the N-well (64) at a first potential and a second lower potential, the second lower potential applied when the pulse circuits (52) are activated. As a result, body effects in the PMOS transistor (58) are minimized while at the same time enabling a boost potential to be applied to the wordline (60).

公开(公告)号：EP0486794A2

公开(公告)日：1992-05-27

申请号：EP91116527.2

申请日：1991-09-27

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Franch, Robert Louis ,  Hwang, Wei

IPC分类号： G11C11/406

CPC分类号： G11C11/406

摘要： A DRAM is described including a plurality of operable storage cells (50), each cell (50) including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. In addition to the plurality of redundant storage cells (50) the DRAM comprises: a decoder (64) for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit (56, 58, 72) is responsive to the first output to enable access of a redundant storage cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells (50) are configured as static storage circuits.

摘要翻译： 描述了包括多个可操作存储单元（50）的DRAM，每个单元（50）包括用于存储指示数据的电荷的电容。 对于大多数可操作单元，对于大多数可操作单元，对于少数可操作单元，电荷倾向于在预定时间间隔T1之后消散到可接受水平以下，在更短的时间间隔T2之后，其消耗低于可接受水平。 DRAM刷新周期之间的时间被调整为大于时间间隔T2。 除了多个冗余存储单元（50）之外，DRAM包括：解码器（64），用于接收可操作的存储器单元的地址，并且如果地址指示少数单元的可操作单元之一，则提供第一输出， 如果地址指示多数的可操作单元之一，则输出第二个输出。 开关电路（56,58,72）响应于第一输出以使得能够访问冗余存储单元并且防止少数存储单元的访问。 在优选实施例中，冗余存储单元（50）被配置为静态存储电路。

公开(公告)号：EP0468135A2

公开(公告)日：1992-01-29

申请号：EP91104396.6

申请日：1991-03-21

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Hwang, Wei

IPC分类号： G11C11/401 ,  G11C8/00

CPC分类号： G11C11/4094 ,  G11C8/18 ,  G11C11/4072 ,  G11C11/4076

摘要： A computer system is described which includes a DRAM having a plurality of memory cells (10, 12) arranged in rows and columns. The system includes a row address buffer (18), and circuitry (24) for generating a row address strobe signal that exhibits both active and inactive levels during each DRAM memory cycle and first and second transitions between those levels. A read-in circuit causes read-in of a row address to the DRAM's row address buffer (18). A delay circuit (54) is responsive to a delayed lagging transition of a row address strobe signal to provide an extended duration control signal which delays an output from the row address buffer (18). A reset/precharge circuit (33) is active during both the inactive row address strobe signal and the extended duration control signal to reset and precharge circuits and memory cells in the DRAM.

摘要翻译： 一种计算机系统被描述，其包括具有以行和列排列的存储器单元（10，12）的多个A DRAM。 该系统包括用于产生行地址选通信号的行地址缓冲器（18）和电路（24）做了展品的水平之间的每个DRAM存储周期以及第一和第二转换期间活动和非活动的水平。 读入电路使读入的行地址的给DRAM行地址缓冲器（18）。 延迟电路（54）响应于行地址选通信信号，以提供给输出哪个延迟来自行地址缓冲器（18）延长时间控制信号的延迟滞后的过渡。 复位/预充电电路（33）是在DRAM两者不活动的行地址选通信号和延长时间控制信号来复位和预充电电路和存储器单元期间有活性。

公开(公告)号：EP0945785A2

公开(公告)日：1999-09-29

申请号：EP99301454.7

申请日：1999-02-26

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Silberman, Joel Abraham

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/322

摘要： A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality of previously fetched instructions, and a sequential address is determined utilizing a last of the plurality of previously fetched instructions. Concurrently with the determination of the target addresses and the sequential address, a select signal specifying one of the plurality of target addresses or the sequential address is generated. The select signal is used to select one of the plurality of target addresses or the sequential address as a memory request address. The memory request address is then transmitted from the processor to the memory so that the memory will supply at least one instruction to the processor. By generating the target addresses and sequential address concurrently with the generation of the selection signal, instruction fetch latency is reduced.

摘要翻译： 公开了一种从存储器取出指令的处理器和方法。 根据本发明的方法，利用多个先前获取的指令来确定多个目标地址，并且利用多个先前获取的指令中的最后一个来确定顺序地址。 同时确定目标地址和顺序地址，产生指定多个目标地址之一或顺序地址的选择信号。 选择信号用于选择多个目标地址之一或顺序地址作为存储器请求地址。 然后，存储器请求地址从处理器发送到存储器，使得存储器将向处理器提供至少一个指令。 通过产生选择信号同时产生目标地址和顺序地址，减少指令提取延迟。

公开(公告)号：EP0550894B1

公开(公告)日：1999-08-04

申请号：EP92122009.1

申请日：1992-12-24

申请人： International Business Machines Corporation

发明人： Bronner, Gary Bela ,  Dhong, Sang Hoo ,  Hwang, Wei ,  Park, Jong Woo ,  Voldman, Steven Howard

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

公开(公告)号：EP0486794A3

公开(公告)日：1994-12-28

申请号：EP91116527.2

申请日：1991-09-27

申请人： International Business Machines Corporation

发明人： Dhong, Sang Hoo ,  Franch, Robert Louis ,  Hwang, Wei

IPC分类号： G11C11/406

CPC分类号： G11C11/406

摘要： A DRAM is described including a plurality of operable storage cells (50), each cell (50) including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. In addition to the plurality of redundant storage cells (50) the DRAM comprises: a decoder (64) for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit (56, 58, 72) is responsive to the first output to enable access of a redundant storage cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells (50) are configured as static storage circuits.