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    BIT SYNCHRONIZATION DETECTION MEANS
    21.
    发明公开
    BIT SYNCHRONIZATION DETECTION MEANS 审中-公开
    BIT同步检测装置

    公开(公告)号：EP1631961A1

    公开(公告)日：2006-03-08

    申请号：EP03727851.2

    申请日：2003-05-27

    申请人： Koninklijke Philips Electronics N.V.

    发明人： STEK, Aalbert ,  SCHEP, Cornelis, M. ,  BAGGEN, Constant, P., M., J. ,  KAHLMAN, Josephus, A., H., M.

    IPC分类号： G11B27/19

    CPC分类号： G11B27/24 ,  G11B7/0053 ,  G11B2220/213 ,  G11B2220/218 ,  G11B2220/2525 ,  G11B2220/2541 ,  G11B2220/2545 ,  G11B2220/2562

    摘要： Detection means for detecting information in a signal, comprising integration means for integrating the signal over time such that the integration means is periodically reset at about the start time reference of a periodic time interval; and a sample&hold circuit for periodically sampling and holding the integrated signal (int) at about an end time reference of the periodic time interval and thereby delivering a further signal (fs). The detection means further comprises a chain (CHDL) of signal time delay elements, an input of the chain (CHDL) being coupled to receive the further signal (fs); and combining means (CBMNS) having combining inputs coupled to signal taps of the chain (CHDL), such that the number of the combining inputs and the position of coupling the combining inputs to the signal taps of the chain (CHDL) correspond to the information in the signal.

    摘要翻译： 用于检测信号中的信息的检测装置，包括用于随时间对信号进行积分的积分装置，使得积分装置在大约周期性时间间隔的开始时间基准周期性地重置; 以及采样和保持电路，用于周期性地在周期性时间间隔的结束时间基准处采样和保持积分信号（int），并由此发送另一个信号（fs）。 检测装置进一步包括信号延时元件的链（CHDL），链的输入（CHDL）被耦合以接收另外的信号（fs）; 和具有耦合到链的信号抽头（CHDL）的组合输入的组合装置（CBMNS），使得组合输入的数量和将组合输入耦合到链的信号抽头（CHDL）的位置对应于信息 在信号中。

    TRELLIS-BASED RECEIVER
    22.
    发明公开
    TRELLIS-BASED RECEIVER 审中-公开
    GRID基于接收器的

    公开(公告)号：EP1576734A1

    公开(公告)日：2005-09-21

    申请号：EP03809809.1

    申请日：2003-09-22

    申请人： Koninklijke Philips Electronics N.V.

    发明人： HEKSTRA, Andries, P. ,  BAGGEN, Constant, P., M., J.

    IPC分类号： H03M13/00

    CPC分类号： H03M13/4161 ,  H03M13/39 ,  H03M13/3955

    摘要： Receivers (1) for receiving encoded block signals and comprising processor systems (2) decode block signals by using Viterbi algorithms for finding a first candidate/path in a trellis (18) and by generating cost signals for finding further candidates/paths in said trellis (18). To reduce storage capacity, cost signals are combined for series of branches and cumulated cost is compared with thresholds. While searching for said further paths, a search for a further path is made in view of cumulated cost exceeding a threshold or not. The insight of indirectly constructing a list of candidates and the basic idea of more directly constructing said list brings more control. These receivers are less complex, and are further improved by introducing increasing thresholds per trellis and successive combining and different trellis directions for generating and cumulating cost signals and combining in a lexicographical order, and using a check sum for list reduction and by making error detections.

    ENHANCED CODING FOR INFORMED DECODERS
    24.
    发明公开
    ENHANCED CODING FOR INFORMED DECODERS 审中-公开
    改进的编码知情解码器

    公开(公告)号：EP1421699A2

    公开(公告)日：2004-05-26

    申请号：EP02745736.5

    申请日：2002-07-04

    申请人： Koninklijke Philips Electronics N.V.

    发明人： TOLHUIZEN, Ludovicus, M., G., M. ,  BLUM, Martinus, W. ,  BAGGEN, Constant, P., M., J.

    IPC分类号： H03M13/15 ,  G11B20/18

    CPC分类号： G11B20/1833 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/37

    摘要： The invention relates to method of encoding address words (a) comprising address symbols (a0, a1, ...,ak-1) into codewords (c) of a code (C) for providing an enhanced error correction capability if at least one information symbol (m1) of information words (m) is known a priori to a decoder decoding received, possibly mutilated codewords (r). The invention relates further to a method of decoding possibly mutilated codewords (r). In order to design a code of which the correction power is enhanced if some information symbols are known to the decoder prior to decoding it is proposed according to the invention that the address words (a) are encoded into information words (m) such that that address words comprising addresses being close to each other share a plurality of information symbols and that said information words (m) are encoded into codewords (c) using a generator matrix (G) which is selected such that the minimum Hamming distance of at least one subcode (C') of said code (C) is larger than the minimum Hamming distance of said code (C) and that a subcode generator matrix (G') of said subcode (C') derives from said generator matrix (G) of said code (C) by omitting the at least one row from said generator matrix (G) corresponding to said at least one a priori known information symbol (m1).

    METHOD OF STORING OR DECODING A STREAM OF BITS
    27.
    发明公开
    METHOD OF STORING OR DECODING A STREAM OF BITS 审中-公开
    保存方法或解码的比特流

    公开(公告)号：EP1314159A1

    公开(公告)日：2003-05-28

    申请号：EP01960687.0

    申请日：2001-08-13

    申请人： Koninklijke Philips Electronics N.V.

    发明人： BAGGEN, Constant, P., M., J. ,  VAN DIJK, Marten, E. ,  COENE, Willem, M., J., M.

    IPC分类号： G11B20/14 ,  G11B20/12 ,  H03M5/14

    CPC分类号： H03M13/27 ,  G11B20/1426 ,  H03M5/14 ,  H03M5/145 ,  H03M13/1515

    摘要： The invention relates to a method of storing a number of data bits of a secondary channel (30) in the frame of a main channel (20) and to a method of decoding a stream of bits relating to a secondary channel (30) embedded in the frames of a main channel (20) into a stream of data bits (62). In order to enable a certain synchronization and to guarantee a fixed amount of storage capacity in the secondary channel as well as to be able to correct deletions or insertions of bits in the secondary channel it is proposed according to the invention to form a secondary frame (11) having a fixed number of frame bits, to fill a fixed part of the secondary frame (11) with data bits (113), an end-bit (114) set to a first bit-value and, if necessary, with filling bits (115) set to a second bit-value, to encode the secondary frame (11) producing encoded data bits (113) and parity bits (112), which are finally embedded in the frame of the main channel (20). The invention relates also to a device for storing a number of data bits of the secondary channel (30) in the frame of a main channel (20) and to a device for decoding a stream of bits of relating to a secondary channel (30) embedded in the frames of a main channel (20).

    TRANSMISSION SYSTEM WITH ADAPTIVE CHANNEL ENCODER AND DECODER
    28.
    发明公开
    TRANSMISSION SYSTEM WITH ADAPTIVE CHANNEL ENCODER AND DECODER 有权
    具有自适应信道编码器和-DEKODER传输系统

    公开(公告)号：EP1000468A2

    公开(公告)日：2000-05-17

    申请号：EP99919484.8

    申请日：1999-05-25

    申请人： Koninklijke Philips Electronics N.V.

    发明人： BAGGEN, Constant, P., M., J.

    IPC分类号： H03M13/35 ,  H04L1/20

    CPC分类号： H04L1/0014 ,  H03M13/05 ,  H04L1/0009 ,  H04L1/0025 ,  H04L1/0026 ,  H04L1/0028 ,  H04L1/0057 ,  H04L1/0072 ,  H04L1/0075 ,  H04L1/0079

    摘要： In a transmission system comprising a transmitter (4) coupled via a transmission channel (10) to a receiver (6). The transmitter (4) comprises a channel encoder (14) for deriving encoded symbols from source symbols. The receiver (6) comprises a channel decoder (28) for reconstructing the source symbols from the signal received from the transmission channel (10). According to the present invention, the transmitter (4) comprises a separate encoder for coding and transmitting a coding property used in the channel encoder (14) to the receiver (6). The receiver (6) is arranged for receiving the encoded coding property from the transmission medium, and the separate channel decoder (26) is arranged for decoding the encoded coding property. The coding property provided by the separate channel decoder (26) is passed to setting means (27) in the channel decoder (28) for setting the coding property of the channel decoder (28).