公开(公告)号：EP3519973A1

公开(公告)日：2019-08-07

申请号：EP17778423.8

申请日：2017-09-21

申请人： Qualcomm Incorporated

发明人： SHANKAR, Harish ,  GARG, Manish

IPC分类号： G06F12/0864 ,  G06F12/0895 ,  G11C15/04

公开(公告)号：EP2756501B1

公开(公告)日：2019-04-03

申请号：EP12766529.7

申请日：2012-09-12

申请人： Qualcomm Incorporated

发明人： GARG, Manish ,  PHAN, Michael ThaiThanh ,  HOFF, David Paul ,  NGUYEN, Quan

IPC分类号： G11C11/419 ,  G11C8/08 ,  G11C11/418

公开(公告)号：EP2514095B1

公开(公告)日：2019-01-16

申请号：EP10795887.8

申请日：2010-12-14

申请人： Qualcomm Incorporated

发明人： GARG, Manish ,  CHAI, Chiaming ,  BRIDGES, Jeffrey Todd

IPC分类号： H03K3/03 ,  H03K5/00

公开(公告)号：EP3283937A1

公开(公告)日：2018-02-21

申请号：EP16720011.2

申请日：2016-04-15

申请人： QUALCOMM Incorporated

发明人： KOLLA, Yeshwant, Nagaraj ,  NATEKAR, Neel, Shashank ,  GARG, Manish

IPC分类号： G06F1/32 ,  G11C5/14 ,  G06F1/26

CPC分类号： G06F1/3234 ,  G06F1/263 ,  G06F1/3287 ,  G11C5/063 ,  G11C5/147 ,  Y02D10/171

摘要： Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail, power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However, if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality, the power rail selection circuit is configured to couple the memory domain to separate memory power rail.

公开(公告)号：EP2891153A1

公开(公告)日：2015-07-08

申请号：EP13795029.1

申请日：2013-10-29

申请人： Qualcomm Incorporated

发明人： SHANKAR, Harish ,  HOFF, David Paul ,  GARG, Manish

IPC分类号： G11C8/16 ,  G11C11/419 ,  G11C8/08 ,  G11C11/418

CPC分类号： G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

摘要： Systems and methods for detecting and suppressing crowbar currents in memory arrays (200). A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers (208a-b). When a simultaneous read and write operation to a first entry (202i) of the memory array is detected, the read operation (206i) to the first entry is suppressed and a dummy read operation (206j) to a second entry (202j) of the memory array is performed. The write operation (204i) to the first entry is allowed to proceed undisturbed.

公开(公告)号：EP2382632A1

公开(公告)日：2011-11-02

申请号：EP10701422.7

申请日：2010-01-21

申请人： QUALCOMM Incorporated

发明人： GARG, Manish ,  CHAI, Chiaming ,  PHAN, Michael, Thai Thanh

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C8/08

摘要： A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.

摘要翻译： 一种存储单元，包括存储元件，耦合到所述存储元件和耦合到所述存储元件的读出电路的写入电路。 至少存储元件的一部分和至少所述写入电路的一部分被使用较厚栅极氧化物制造的功能和至少读出电路的一部分使用较薄栅极氧化物官能制造。

公开(公告)号：EP1989562B1

公开(公告)日：2010-09-22

申请号：EP07757747.6

申请日：2007-03-01

申请人： QUALCOMM Incorporated

发明人： GARG, Manish ,  HAMDAN, Fadi Adel

IPC分类号： G01R31/3185 ,  G11C29/00 ,  H03K3/037

CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/32

摘要： A dual-path, multimode sequential storage element (SSE) (10) is described herein. In one example, the dual-path, multimode SSE comprises first (14) and second (12) sequential storage elements, a data input, a data output, and a selector mechanism (16). The first and second sequential storage elements (14, 12) each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism (16) is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element (14) and the second sequential storage element comprises a master-slave storage element (12).

公开(公告)号：EP1989562A1

公开(公告)日：2008-11-12

申请号：EP07757747.6

申请日：2007-03-01

申请人： QUALCOMM Incorporated

发明人： GARG, Manish ,  HAMDAN, Fadi Adel

IPC分类号： G01R31/3185 ,  G11C29/00 ,  H03K3/037

CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/32

摘要： A dual-path, multimode sequential storage element (SSE) (10) is described herein. In one example, the dual-path, multimode SSE comprises first (14) and second (12) sequential storage elements, a data input, a data output, and a selector mechanism (16). The first and second sequential storage elements (14, 12) each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism (16) is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element (14) and the second sequential storage element comprises a master-slave storage element (12).