利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.012 秒)

    PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS
    1.
    发明公开
    PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS 有权
    在数据访问之前静态随机存取存储器（SRAM）中的预充电二线以降低泄漏功率，以及相关的系统和方法

    公开(公告)号：EP2976770A1

    公开(公告)日：2016-01-27

    申请号：EP14727682.8

    申请日：2014-05-02

    申请人： Qualcomm Incorporated

    发明人： CHAI, Chiaming ,  GE, Shaoping ,  LILES, Stephen, Edward ,  GARG, Kunal

    IPC分类号： G11C11/412 ,  G11C11/413 ,  G11C7/12 ,  G11C7/10

    CPC分类号： G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

    摘要： Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

    摘要翻译： 这里公开的实施例包括用于在数据访问之前对静态随机存取存储器（SRAM）中的位线进行预充电以减少泄漏功率的方法和设备。 存储器访问逻辑电路接收包括要在SRAM的SRAM数据阵列的第一数据存取路径中存取的数据入口地址的存储器存取请求。 SRAM还包括设置在第一数据存取路径外的第二数据存取路径中的预充电电路。 预充电电路被配置为使能SRAM存储器访问请求的一部分的SRAM数据阵列的预充电，以避免在空闲期间预充电SRAM数据阵列中的位线以减少泄漏功率。 预充电电路可以在数据访问之前启用对SRAM数据阵列的预充电，使得预充电电路不向第一数据存取路径增加等待时间。

    CIRCUIT AND METHOD FOR SUBDIVIDING A CAMRAM BANK BY CONTROLLING A VIRTUAL GROUND
    2.
    发明授权
    CIRCUIT AND METHOD FOR SUBDIVIDING A CAMRAM BANK BY CONTROLLING A VIRTUAL GROUND 有权
    电路及方法camRAM，银行通过控制虚拟地细分

    公开(公告)号：EP1941513B1

    公开(公告)日：2010-11-10

    申请号：EP06846190.4

    申请日：2006-10-30

    申请人： QUALCOMM Incorporated

    发明人： PHAN, Michael, ThaiThanh ,  CHAI, Chiaming ,  BRIDGES, Jeffrey, Todd ,  FISCHER, Jeffrey, Herbert

    IPC分类号： G11C15/04

    CPC分类号： G11C15/00 ,  G11C8/12 ,  G11C15/04

    摘要： A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

    CIRCUITS FOR VOLTAGE OR CURRENT BIASING STATIC RANDOM ACCESS MEMORY (SRAM) BITCELLS DURING SRAM RESET OPERATIONS, AND RELATED SYSTEMS AND METHODS
    5.
    发明公开
    CIRCUITS FOR VOLTAGE OR CURRENT BIASING STATIC RANDOM ACCESS MEMORY (SRAM) BITCELLS DURING SRAM RESET OPERATIONS, AND RELATED SYSTEMS AND METHODS 审中-公开
    电压或电流偏置静态随机存取存储器（SRAM）-BITZELLEN器电路。在手术SRAM RESET及相关系统和方法

    公开(公告)号：EP3028282A2

    公开(公告)日：2016-06-08

    申请号：EP14755206.1

    申请日：2014-07-29

    申请人： Qualcomm Incorporated

    发明人： CHAI, Chiaming ,  MAURYA, Satendra Kumar

    IPC分类号： G11C11/417 ,  G11C11/419 ,  G11C7/20 ,  G11C11/412

    CPC分类号： G11C11/412 ,  G11C7/20 ,  G11C11/417 ,  G11C11/419

    摘要： Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.

    REDIRECTING DATA FROM A DEFECTIVE DATA ENTRY IN MEMORY TO A REDUNDANT DATA ENTRY PRIOR TO DATA ACCESS, AND RELATED SYSTEMS AND METHODS
    6.
    发明公开
    REDIRECTING DATA FROM A DEFECTIVE DATA ENTRY IN MEMORY TO A REDUNDANT DATA ENTRY PRIOR TO DATA ACCESS, AND RELATED SYSTEMS AND METHODS 审中-公开
    数据转移与商店一个错误的数据录入冗余信息项的数据访问之前和相关系统和方法

    公开(公告)号：EP2994914A1

    公开(公告)日：2016-03-16

    申请号：EP14730305.1

    申请日：2014-05-06

    申请人： Qualcomm Incorporated

    发明人： CHAI, Chiaming ,  GE, Shaoping ,  LILES, Stephen, Edward

    IPC分类号： G11C29/00

    摘要： Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

    CIRCUITS, SYSTEMS, AND METHODS FOR DYNAMIC VOLTAGE LEVEL SHIFTING
    7.
    发明公开
    CIRCUITS, SYSTEMS, AND METHODS FOR DYNAMIC VOLTAGE LEVEL SHIFTING 有权
    电路系统和动态电压电平变化的方法

    公开(公告)号：EP2556589A1

    公开(公告)日：2013-02-13

    申请号：EP11716692.6

    申请日：2011-04-05

    申请人： Qualcomm Incorporated

    发明人： LILES, Stephen Edward ,  CHAI, Chiaming ,  MAMILETI, Lakshmikant

    IPC分类号： H03K3/356 ,  G11C11/419

    CPC分类号： H03K3/356182 ,  H03K3/356113

    摘要： Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.

    A PULSE CLOCK GENERATION LOGIC WITH BUILT-IN LEVEL SHIFTER AND PROGRAMMABLE RISING EDGE AND PULSE WIDTH
    10.
    发明公开
    A PULSE CLOCK GENERATION LOGIC WITH BUILT-IN LEVEL SHIFTER AND PROGRAMMABLE RISING EDGE AND PULSE WIDTH 有权
    具有集成幻灯片，可编程上升沿和脉冲宽度脉冲时钟产生逻辑电平

    公开(公告)号：EP2831694A1

    公开(公告)日：2015-02-04

    申请号：EP13715579.2

    申请日：2013-03-28

    申请人： Qualcomm Incorporated

    发明人： GE, Shaoping ,  CHAI, Chiaming ,  LILES, Stephen Edward ,  NGUYEN, Lam V. ,  FISCHER, Jeffrey Herbert

    IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C11/419

    CPC分类号： G06F1/04 ,  G11C7/222 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

    摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit (100) includes a selective delay logic (102) to provide a programmable rising edge delay of the pulse clock (114), a selective pulse width widening logic (110) to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

    摘要翻译： 系统和用于产生脉冲的时钟具有可编程边缘并且被配置用于改变不同的存储器存取操作的要求的脉冲宽度的方法。 脉冲时钟生成电路包括一选择性延迟逻辑，用于提供所述脉冲时钟的可编程上升沿延迟，一个选择脉冲宽度加宽逻辑，以提供所述脉冲时钟的可编程脉冲宽度，和一个内置的电平移位器用于转换电压 脉冲时钟的水平。 对于读手术的上升沿延迟被编程以在预期readArray接入延迟对应，以及用于操作的写入脉冲宽度被编程比用于读操作的脉冲宽度得以体现。