公开(公告)号：EP4381506A1

公开(公告)日：2024-06-12

申请号：EP22817440.5

申请日：2022-10-26

Applicant: Google LLC

Inventor： The designation of the inventor has not yet been filed

IPC: G11C29/02 ,  G11C29/00 ,  G11C29/12 ,  G11C29/24 ,  G11C29/28 ,  G11C29/44 ,  G11C29/26 ,  G11C29/32

CPC classification number: G11C29/81 ,  G11C29/86 ,  G11C29/4401 ,  G11C29/1201 ,  G11C2029/120820130101 ,  G11C29/28 ,  G11C2029/260220130101 ,  G11C2029/440220130101 ,  G11C29/022 ,  G11C29/025 ,  G11C29/32 ,  G11C2029/320220130101 ,  G11C29/24 ,  G11C29/812 ,  G11C29/027

公开(公告)号：EP3388849A1

公开(公告)日：2018-10-17

申请号：EP17401042.1

申请日：2017-04-11

Applicant: Karlsruher Institut für Technologie

Inventor： Oboril, Fabian ,  Bishnoi, Rajendra ,  Tahoori, Mehdi B.

IPC: G01R31/303 ,  G11C29/00 ,  G01R1/07

CPC classification number: G01R31/303 ,  G01R1/07 ,  G11C29/32 ,  G11C29/56012 ,  G11C29/56016 ,  G11C2029/3202

Abstract: Method (100, 400) for testing at least one electronic assembly, comprising: Providing at least one electronic assembly, wherein said electronic assembly comprises at least n magnetic storage cells, and wherein n is a natural number starting with 1, corresponding to positive integers; and at least one testing device with n read write electronics, wherein said read-write electronics are adapted to said at least one said storage cell (310); Arranging said testing device above said electronic assembly so that each of said read-write electronics is located without contact on top of one respective storage cell (320); Writing at least one of said storage cells by means of said testing device (330); and Reading out at least said storage cell (420) by means of said testing device (340).

公开(公告)号：EP2693441A1

公开(公告)日：2014-02-05

申请号：EP12178649.5

申请日：2012-07-31

Applicant: eMemory Technology Inc.

Inventor： Tsai, Yu-Hsiung ,  Huang, Po-Hao ,  Shen, Chiun-Chi ,  Huang, Jie-Hau

IPC: G11C29/32

CPC classification number: G11C29/32

Abstract: The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.

Abstract translation: 本发明提供一种存储器架构和相关联的串行直接访问（SDA）电路。 存储器架构包括并行接口和串行直接访问（SDA）电路的存储器。 SDA电路包括一个使能引脚，一个串行引脚和一个自动测试模块。 使能引脚接收使能位，其中响应于使能位选择性地使能和禁止SDA电路。 当SDA电路使能时，串行引脚顺序中继多个串行位，使得每个串行位与并行接口的并行引脚之一相关联; 此外，自动测试模块可以对与串行位相关联的存储器执行内置测试。

公开(公告)号：EP2619765A1

公开(公告)日：2013-07-31

申请号：EP11771296.8

申请日：2011-09-21

Applicant: Qualcomm Incorporated

Inventor： RAO, Hari M. ,  YOON, Sei Seung ,  CHEN, Nan

IPC: G11C29/32 ,  G01R31/3185

CPC classification number: G01R31/318541 ,  G11C11/417 ,  G11C29/32

Abstract: A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.

公开(公告)号：EP0921528B1

公开(公告)日：2005-10-19

申请号：EP98303712.8

申请日：1998-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chai, Joon-Wan ,  Kyung, Kye-Hyun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C29/48

Abstract: A memory device includes N pipe line blocks (12,22) for inputting N memory blocks (10,20) and a plurality of data outputs from each of the memory blocks to sequentially output the input data, where N is a natural number, and connects an output line of a ith pipe line block to an input line of a (i + 1)th pipe line block. such that if the device enters a direct access test mode, data sequentially output from an ith pipe line block is input to an (i + 1)th pipe line block, where 1 is a natural number smaller than N. Accordingly, data latched in N pipe line blocks are output using one data output pin, to thereby reduce the number of data output pins used for a direct access mode test to 1/N.

公开(公告)号：EP0933644B1

公开(公告)日：2005-05-25

申请号：EP99300685.7

申请日：1999-01-29

Applicant: STMicroelectronics Limited

Inventor： Maccormack, Andrew

IPC: G01R31/3185 ,  G11C29/00

CPC classification number: G11C29/32 ,  G01R31/318536

公开(公告)号：EP0929895B1

公开(公告)日：2001-11-28

申请号：EP97910744.8

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

公开(公告)号：EP1097459A1

公开(公告)日：2001-05-09

申请号：EP00929695.5

申请日：2000-05-12

Applicant: STMicroelectronics, Ltd.

Inventor： BARNES, William, Bryan

IPC: G11C29/00

CPC classification number: G11C29/40 ,  G11C29/32

Abstract: The present invention relates to a memory having sense amplifiers and data latches, the data latches being used in a test mode to form a signature register. In a normal operation mode, the data latches are form write data latches.

公开(公告)号：EP1089085A1

公开(公告)日：2001-04-04

申请号：EP00308376.3

申请日：2000-09-25

Applicant: STMicroelectronics, Inc.

Inventor： Edwards, David Alan ,  Wright, Stephen James

IPC: G01R31/3185 ,  G11C29/00

CPC classification number: G11C29/32 ,  G01R31/318533 ,  G06F11/3656 ,  G11C29/003

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

Abstract translation: 提供了一种用于与集成电路通信的系统和方法，其允许集成电路与外部系统通信调试信息和系统总线事务信息。 该系统可以包括在集成电路和外部系统之间提供流量控制的接口协议。 该系统可以包括用于传送信息的高速链路和/或JTAG链路。 链路可以由调试电路自动选择，或由片上设备或外部系统选择。 高速链路可实时追踪跟踪信息。 链路可以是存储器映射的，使得连接到系统总线的片上设备和其他设备可以访问外部系统。 高速链路也可以以与处理器或系统总线的速率整体耦合的速率工作。 此外，高速链路可以适应于响应于系统总线或处理器的操作速度的变化而改变速度。 JTAG接口可以使用标准的JTAG组件和指令，使得采用这些组件和指令的外部设备（例如调试适配器）可以被重新用于不同的集成电路类型。 通过JTAG或高速链路发送的信息可以被压缩以优化链路的可用带宽。 此外，处理器控制信号可以通过允许外部系统操纵和监视处理器及其相关模块的操作的链路传送。

公开(公告)号：EP0981134A3

公开(公告)日：2000-05-31

申请号：EP99402038.6

申请日：1999-08-11

Applicant: SONY CORPORATION

Inventor： Koga, Kiyokazu, c/o Sony Corporation ,  Arai, Hiroaki, c/o Sony Corporation

IPC: G11C29/00 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/273

CPC classification number: G06F11/2236 ,  G01R31/31908 ,  G11C29/32

Abstract: The present invention provides a signal processing apparatus having at least a boundary scan chain (27, 28) for carrying out a boundary scan test, a CPU (24) capable of being controlled by the boundary scan chain, a non-volatile memory (22) for storing an operating program of the CPU and necessary data, and an input terminal for inputting data and other control signals from the outside to the boundary scan chain, a register (29) for holding data transferred from the boundary scan chain and a memory for holding the data read from the register. During data rewriting, based on the control of the boundary scan chain, a rewriting program is input via the input terminal from a writing device to the boundary scan chain and then stored in the memory through the register, the CPU inputs rewriting data to write it into the non-volatile memory based on the control of the rewriting program stored in the memory.