公开(公告)号：EP0708482A3

公开(公告)日：1997-03-26

申请号：EP95116353.4

申请日：1995-10-17

申请人： SILICONIX Incorporated

发明人： Williams, Richard K. ,  Yilmaz, Hamza ,  Cornell, Michael E. ,  Chen, Jun Wei

IPC分类号： H01L21/8249 ,  H01L27/06

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7835 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或任何期望的组合 这些都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：EP0722189A2

公开(公告)日：1996-07-17

申请号：EP95120355.3

申请日：1995-12-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Hshieh, Fwu-Iuan

IPC分类号： H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7811

摘要： A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

公开(公告)号：EP0492991A3

公开(公告)日：1993-01-07

申请号：EP91311810.5

申请日：1991-12-19

申请人： SILICONIX Incorporated

发明人： Hshieh, Fwu-Iuan ,  Chang, Mike ,  Yilmaz, Hamza

IPC分类号： H01L21/322 ,  H01L29/167 ,  H01L21/336 ,  H01L29/784

CPC分类号： H01L29/7802 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66712 ,  H01L29/7811

摘要： A gettering method is proposed for minimizing defects in the shallow junctions used for forming the short channel, including the use of thin dry oxide, a field shaping P⁺- diffusion to enhance breakdown voltage, and TCA (trichloroethane) gettering. Gate-source leakage is reduced with extrinsic gettering on the poly backside, and intrinsic gettering due to the choice of starting material. A submicron channel length (144) is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. The method is used to fabricate a double-diffused integrated circuit cell.

公开(公告)号：EP1119036B1

公开(公告)日：2003-04-02

申请号：EP01107549.6

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Cornell, Michael E. ,  Williams, Richard K. ,  Chen, Jue Wei

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

公开(公告)号：EP0589675B1

公开(公告)日：2002-07-10

申请号：EP93307457.7

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Williams, Richard K. ,  Cornell, Michael E. ,  Chen, Jue Wei

IPC分类号： H01L27/06 ,  H01L21/82

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

公开(公告)号：EP1119051A1

公开(公告)日：2001-07-25

申请号：EP01107548.8

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Cornell, Michael E. ,  Williams, Richard K. ,  Chen, Jue Wei

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

摘要： A vertical transistor structure, comprising a substrate layer of a semiconductor material of a first conductivity type; an epitaxial layer of a semiconductor material of a second conductivity type opposite said first conductivity type, said epitaxial layer disposed over said substrate layer, said epitaxial layer having an upper surface; a collector buries region extending downward into said substrate layer and also extending upward into said epitaxial layer, said collector buried region having an upper surface disposed below said upper surface of said epitaxial layer, said collector buried region being of a semiconductor material of said second conductivity type; a collector sinker region extending downward into said epitaxial layer from said upper surface of said epitaxial layer, said collector sinker region contracting said collector buried region, said collector buried region and said collector sinker region separating a collector portion of said epitaxial layer from other portions of said epitaxial layer and from said substrate layer, said collector sinker region being of a semiconductor material of said second conductivity type; a base region disposed in said collector portion of said epitaxial layer, said base region extending downward into said collector portion of said epitaxial layer from said upper surface of said epitaxial layer, said base region being of a semiconductor material of said first conductivity type; a polysilicon layer disposed over said upper surface of said epitaxial layer; a base contact region disposed in said base region, said base contact region having an edge which is self-aligned with a first edge of said polysilicon layer, said base contact region being of a semiconductor materia of said first conductivity type; and an emitter region disposed in said base region, said emitter region having an edge which is self-aligned with a second edge of said polysilicon layer, said emitter being of a semiconductor material of said second conductivity type.

公开(公告)号：EP1119050A1

公开(公告)日：2001-07-25

申请号：EP01107552.0

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Cornell, Michael E. ,  Williams, Richard K. ,  Chen, Jue Wei

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

摘要： A method for providing a plurality of buries zener diodes and an MOS transistor on a single wafer, said wafer comprising an epitaxial layer having an upper surface, said epitaxial layer being doped with a dopant of a first conductivity type, said MOS transistor being formed in an MOS region of said wafer, said plurality of buried zener diodes being formed in a zener region of said wafer, said method comprising the steps of: (a) forming a plurality of laterally separated first zener portions into upper surface of said epitaxial layer in said zener region, each of said first zener portions being doped with a dopant of a second conductivity type opposite said first conductivity type; (b) performing an ion implantation step with a dopant of said first conductivity type to form simultaneously a source and a drain in said MOS region, said source being lightly doped and said drain being lightly doped, and to form simultaneously at least one relatively lightly doped second zener portion in said zener region; and (c) performing an ion implantation step with a dopant of said first conductivity type to form simultaneously a plurality of relatively highly doped third zener portions into said zener region, to dope said source, and to form simultaneously a drain contact region within said drain, each of said plurality of relatively highly dopes third zener portions corresponding with and making contact with one of said first zener portions to form one of said plurality of buried zener diodes, said at least one relatively lightly doped second zener portion surrounding in a laterally orientated plane at least one of said plurality of first zener portions.

摘要翻译： 一种横向晶体管结构，包括：具有第一导电类型的半导体材料的第一半导体层; 设置在所述第一半导体层上的第二半导体层，所述第二半导体层具有上表面; 设置在所述第二半导体层的所述上表面上的场氧化物层; 设置在所述场氧化物层下面的场注入区域，所述场注入区域是所述第一导电类型的半导体材料，所述场注入区域被轻掺杂; 从所述第二半导体层的所述上表面延伸到所述第二半导体层的漏极区，所述漏极区接触所述场注入区，所述漏区是所述第一导电类型的半导体材料; 源区域从所述第二半导体层的所述上表面延伸到所述第二半导体中，所述源极区域与所述场注入区域横向分离，所述源区域是所述第一导电类型的半导体材料; 从所述第二半导体层的所述上表面延伸到所述第二半导体中的体接触区域，所述体接触区域与所述源区域接触，所述源区域设置在所述体接触区域和所述场注入区域之间，所述体接触区域为 与所述第一导电类型相反的第二导电类型的半导体材料; 从所述主体接触区域和所述源极区域下方延伸的主体区域，所述主体区域在所述源区域和所述场注入区域之间延伸，以在所述源区域和所述场植入物之间的所述第二半导体层的所述上表面处形成沟道区域 所述体接触区域是所述第二半导体类型的半导体材料，所述体接触区域与所述场注入区域之间的所述第二半导体层的漂移区部分与所述源极区域和所述场注入区域之间分离。 以及多晶硅栅极层，所述多晶硅栅极层从所述源极区上方的所述沟道区上方延伸，并且在所述第二半导体层的所述漂移区部分上方延伸。

公开(公告)号：EP0895290A1

公开(公告)日：1999-02-03

申请号：EP98111605.6

申请日：1995-12-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Hshieh, Fwu-Iuan, c/o Siliconix Incorporated

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7811

摘要： A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

摘要翻译： 用于沟槽MOSFET或其他半导体器件的端接结构（沿着晶体管周边或管芯边缘）可以防止不期望的表面沟道现象，而不需要任何额外的掩模步骤来形成通道停止。 该结构特别适用于P沟道MOSFET。 在现有技术中，掩模限定了掺杂通道停止。 而是在有源区域掩蔽处理之后进行P型离子的覆盖离子注入。 因此，这种掺杂沟道停止终止在场氧化物的制造期间实际上被掩蔽。 在另一个版本中，通道停止端接是在MOSFET的端接区域中形成的另外的沟槽。 沟槽通常衬有氧化物并填充有延伸到管芯边缘的导电多晶硅场板。 在另一个版本中，掺杂和沟槽通道停止被组合使用。 通过在模具表面上设置覆盖它们的场板来增强通道挡块。

公开(公告)号：EP0616372A3

公开(公告)日：1996-08-14

申请号：EP94301847.3

申请日：1994-03-15

申请人： SILICONIX Incorporated

发明人： Hshieh, Fwu-Iuan ,  Chang, Mike F. ,  Yilmaz, Hamza

IPC分类号： H01L29/784 ,  H01L29/60

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  Y10S148/103 ,  Y10S438/965

摘要： A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

公开(公告)号：EP0589675A2

公开(公告)日：1994-03-30

申请号：EP93307457.7

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Williams, Richard K. ,  Cornell, Michael E. ,  Chen, Jue Wei

IPC分类号： H01L27/06 ,  H01L21/82

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

摘要： A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种同时形成高质量互补双极晶体管，相对高电压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器或这些的任何期望组合的方法，全部在同一集成电路芯片上 。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。