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    Method of manufacturing a semiconductor integrated circuit device
    1.
    发明公开
    Method of manufacturing a semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：EP0392480A3

    公开(公告)日：1990-12-27

    申请号：EP90106894.0

    申请日：1990-04-10

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Sasaki, Goro, c/o Yokohama Works

    IPC分类号： H01L27/144 ,  H01L31/105

    CPC分类号： H01L21/8252 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/0605 ,  H01L27/1443 ,  H01L31/105 ,  Y10S148/072 ,  Y10S148/103

    摘要： There is disclosed a method of manufacturing an integrated circuit, comprising: the first step of growing a first epitaxial crystal on a compound semiconductor substrate (1), removing an unnecessary region of the first epitaxial crystal to form a residual portion (5), and covering the residual portion (5) with a selective growth mask (6), the second step of growing a second epitaxial crystal on an exposed substrate portion (1), removing an unnecessary portion of the second epitaxial crystal to form a residual portion (15) of the second epitaxial crystal, and covering the residual portion (15) of the second epitaxial crystal with a selective growth mask (19), and the third step of growing a third epitaxial crystal (11) on an exposed substrate portion (1) and removing an unnecessary region of the third epitaxial crystal (11), wherein the first to third epitaxial crystal (5,15,11) form any one of a pin photodiode crystal (16), a heterojunction bipolar transistor crystal (17), and a high electron mobility transistor crystal (18), and are different from each other.

    BRIGHT FIELD WAFER TARGET
    2.
    发明公开
    BRIGHT FIELD WAFER TARGET 失效
    明亮的场景晶圆目标

    公开(公告)号：EP0691033A1

    公开(公告)日：1996-01-10

    申请号：EP94911616.0

    申请日：1994-03-15

    申请人： VLSI TECHNOLOGY, INC.

    发明人： LEROUX, Pierre

    IPC分类号： H01L21 ,  G03F9

    CPC分类号： G03F9/7076 ,  H01L21/681 ,  Y10S148/103 ,  Y10S438/975

    摘要： A composite target used in alignment of layers (22-26) on a wafer uses alignment marks placed in a target area (9, 10). First alignment marks (11) are composed of material from a first layer (22) placed on the wafer. As subsequent layers (22-26) are placed on the wafer, alignment marks composed of material from the subsequent layers (23-26) are placed within the target area (9, 10). For example, alignment marks (12) composed of material from a second layer (23) are each placed adjacent to one of the alignment marks composed of material from the first layer (22). Alignment marks (13) composed of material from a third layer (24) are each placed adjacent to one of the alignment marks composed of material from the second layer (23). Alignment marks (14) composed of material from a fourth layer (25) are each placed adjacent to the alignment marks composed of material from the third layer (24). And so on. The alignment marks (11-15) are, for example, each rectangular in shape.

    摘要翻译： 用于对齐晶片上的层（22-26）的复合靶使用放置在目标区域（9,10）中的对准标记。 第一对准标记（11）由放置在晶片上的第一层（22）的材料构成。 随着随后的层（22-26）被放置在晶片上，由来自后续层（23-26）的材料构成的对准标记被放置在目标区域（9,10）内。 例如，由来自第二层（23）的材料构成的对准标记（12）各自与由来自第一层（22）的材料构成的对准标记之一相邻放置。 由来自第三层（24）的材料构成的对准标记（13）分别与由来自第二层（23）的材料构成的对准标记之一相邻放置。 由来自第四层（25）的材料构成的对准标记（14）各自与由来自第三层（24）的材料构成的对准标记相邻放置。 等等。 对准标记（11-15）例如是每个矩形的形状。

    Method of manufacturing a semiconductor integrated circuit device
    7.
    发明公开
    Method of manufacturing a semiconductor integrated circuit device 失效
    Herstellungsverfahren einer integrierten Halbleiterschaltung。

    公开(公告)号：EP0392480A2

    公开(公告)日：1990-10-17

    申请号：EP90106894.0

    申请日：1990-04-10

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Sasaki, Goro, c/o Yokohama Works

    IPC分类号： H01L27/144 ,  H01L31/105

    CPC分类号： H01L21/8252 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/0605 ,  H01L27/1443 ,  H01L31/105 ,  Y10S148/072 ,  Y10S148/103

    摘要： There is disclosed a method of manufacturing an integrated circuit, comprising: the first step of growing a first epitaxial crystal on a compound semiconductor substrate (1), removing an unnecessary region of the first epitaxial crystal to form a residual portion (5), and covering the residual portion (5) with a selective growth mask (6), the second step of growing a second epitaxial crystal on an exposed substrate portion (1), removing an unnecessary portion of the second epitaxial crystal to form a residual portion (15) of the second epitaxial crystal, and covering the residual portion (15) of the second epitaxial crystal with a selective growth mask (19), and the third step of growing a third epitaxial crystal (11) on an exposed substrate portion (1) and removing an unnecessary region of the third epitaxial crystal (11), wherein the first to third epitaxial crystal (5,15,11) form any one of a pin photodiode crystal (16), a heterojunction bipolar transistor crystal (17), and a high electron mobility transistor crystal (18), and are different from each other.

    摘要翻译： 公开了一种制造集成电路的方法，包括：在化合物半导体衬底（1）上生长第一外延晶体的第一步骤，去除第一外延晶体的不需要的区域以形成残余部分（5），以及 用选择性生长掩模（6）覆盖残留部分（5），第二步骤，在暴露的衬底部分（1）上生长第二外延晶体，去除第二外延晶体的不需要的部分以形成剩余部分（15 ），并且用选择性生长掩模（19）覆盖第二外延晶体的残余部分（15），以及在暴露的基板部分（1）上生长第三外延晶体（11）的第三步骤， 以及去除所述第三外延晶体（11）的不需要的区域，其中所述第一至第三外延晶体（5,15,11）形成pin光电二极管晶体（16），异质结双极晶体管晶体（17）中的任一个，以及 高e 晶体管迁移率晶体管晶体（18），并且彼此不同。

    Short channel trenched DMOS transistor
    9.
    发明公开
    Short channel trenched DMOS transistor 失效
    沟槽DMOS晶体管具有短通道。

    公开(公告)号：EP0616372A3

    公开(公告)日：1996-08-14

    申请号：EP94301847.3

    申请日：1994-03-15

    申请人： SILICONIX Incorporated

    发明人： Hshieh, Fwu-Iuan ,  Chang, Mike F. ,  Yilmaz, Hamza

    IPC分类号： H01L29/784 ,  H01L29/60

    CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  Y10S148/103 ,  Y10S438/965

    摘要： A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    10.
    发明授权
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
    制造半导体器件的方法

    公开(公告)号：EP0144444B1

    公开(公告)日：1992-02-26

    申请号：EP84902071.4

    申请日：1984-05-25

    申请人： SONY CORPORATION

    发明人： OUCHI, Norikazu Sony Corporation ,  KAYANUMA, Akio Sony Corporation ,  ASANO, Katsuaki Sony Corporation

    IPC分类号： H01L29/72

    CPC分类号： H01L21/033 ,  H01L29/72 ,  H01L29/7325 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/103 ,  Y10S148/106

    摘要： A primary object of the present invention is to manufacture a semiconductor device which has both a high performance and a high degree of integration. The method according to this invention comprises the steps of forming a semiconductor layer (30), (31), (31') provided with recesses in its surface, forming a nitride layer (35) within the recesses, forming an oxide layer (39) over the surface of the semiconductor layer (30) using the nitride layer (35) as a mask, removing the nitride layer (35), and introducing an impurity into the semiconductor layers (31), (31') using the oxide layer (39) as a mask. This method makes it possible to form smaller elements, and is most suitable for the manufacture of an IC device which has both a high performance and a high degree of integration.

    摘要翻译： 本发明的主要目的是制造兼具高性能和高集成度的半导体器件。 根据本发明的方法包括以下步骤：形成在其表面上设置有凹槽的半导体层（30），（31），（31'），在凹槽内形成氮化物层（35），形成氧化物层 ）使用氮化物层（35）作为掩模在半导体层（30）的表面上方去除氮化物层（35），并且使用氧化物层（31'）将杂质引入半导体层（31） （39）作为面具。 该方法使得可以形成更小的元件，并且最适合于制造兼具高性能和高集成度的IC器件。