公开(公告)号：EP1119051B1

公开(公告)日：2005-06-01

申请号：EP01107548.8

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Cornell, Michael E. ,  Williams, Richard K. ,  Chen, Jue Wei

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L27/06 ,  H01L21/8249

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

公开(公告)号：EP0616372B1

公开(公告)日：2002-06-12

申请号：EP94301847.3

申请日：1994-03-15

申请人： SILICONIX Incorporated

发明人： Hshieh, Fwu-Iuan ,  Chang, Mike F. ,  Yilmaz, Hamza

IPC分类号： H01L29/772

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  Y10S148/103 ,  Y10S438/965

摘要： A trenched transistor comprises a substrate defining a trench containing a conductive gate electrode, and a body region of a second conductivity type extending from a principal surface of the substrate adjacent to the trench into the substrate to a depth less than that of the trench. A portion of the body region immediately adjacent to the trench is shallower with respect to the principal surface than is another portion of the body region away from the trench. An edge of the body region immediately adjacent the trench slopes such that a portion of the edge immediately adjacent the trench is closer to the principal surface. A source region of the first conductivity type is formed in the substrate.

公开(公告)号：EP0722189B1

公开(公告)日：2001-04-25

申请号：EP95120355.3

申请日：1995-12-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Hshieh, Fwu-Iuan

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7811

摘要： A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

公开(公告)号：EP0492991B1

公开(公告)日：1999-06-23

申请号：EP91311810.5

申请日：1991-12-19

申请人： SILICONIX Incorporated

发明人： Hshieh, Fwu-Iuan ,  Chang, Mike ,  Yilmaz, Hamza

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66712 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gettering. Gate-source leakage is reduced with extrinsic gettering on the poly backside, and intrinsic gettering due to the choice of starting material.

公开(公告)号：EP0616372A2

公开(公告)日：1994-09-21

申请号：EP94301847.3

申请日：1994-03-15

申请人： SILICONIX Incorporated

发明人： Hshieh, Fwu-Iuan ,  Chang, Mike F. ,  Yilmaz, Hamza

IPC分类号： H01L29/784 ,  H01L29/60

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  Y10S148/103 ,  Y10S438/965

摘要： A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

摘要翻译： 沟槽晶体管包括限定包含导电栅电极的沟槽的衬底和从邻近沟槽的衬底的主表面延伸到衬底的深度小于沟槽的深度的第二导电类型的体区。 与沟槽紧邻的身体区域的一部分相对于主表面比远离沟槽的身体区域的另一部分更浅。 紧邻沟槽的身体区域的边缘倾斜，使得紧邻沟槽的边缘的一部分更靠近主表面。 在衬底中形成第一导电类型的源区。

公开(公告)号：EP0567341A1

公开(公告)日：1993-10-27

申请号：EP93303169.2

申请日：1993-04-22

申请人： SILICONIX INCORPORATED

发明人： Yilmaz, Hamza

IPC分类号： H01L29/772 ,  H01L29/72

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/7811

摘要： The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

摘要翻译： 本发明提供了栅极屏蔽区域和功率器件的有源电池之间的栅极缓冲区域。 该栅极缓冲区可以例如是从外延层的上表面延伸到外延层中的相对窄的带状掺杂区域。 栅极屏蔽区域通过相对高阻抗的连接与功率器件的源极连接。 另一方面，栅极缓冲区域以相对较低的阻抗连接与源极连接。 该相对低阻抗的连接例如可以是从外围层表面的金属源电极到栅极缓冲区域的基本上直接的金属化连接。

公开(公告)号：EP0708482B1

公开(公告)日：2004-12-22

申请号：EP95116353.4

申请日：1995-10-17

申请人： SILICONIX Incorporated

发明人： Williams, Richard K. ,  Yilmaz, Hamza ,  Cornell, Michael E. ,  Chen, Jun Wei

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7835 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

公开(公告)号：EP1119043A2

公开(公告)日：2001-07-25

申请号：EP01107550.4

申请日：1993-09-21

申请人： SILICONIX Incorporated

发明人： Yilmaz, Hamza ,  Cornell, Michael E. ,  Williams, Richard K. ,  Chen, Jue Wei

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/42368 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085 ,  H01L2924/00

摘要： A lateral transistor structure, comprising: a first semiconductor layer being of a semiconductor material of a first conductivity type; a second semiconductor layer disposed on said first semiconductor layer, said second semiconductor layer having an upper surface; a field oxide layer disposed on said upper surface of said second semiconductor layer; a field implant region disposed underneath said field oxide layer, said field implant region being of a semiconductor material of said first conductivity type, said field implant region being lightly doped; a drain region extending into said second semiconductor layer from said upper surface of said second semiconductor layer, said drain region contacting said field implant region, said drain region being of a semiconductor material of said first conductivity type; a source region extending into said second semiconductor from said upper surface of said second semiconductor layer, said source region being laterally separated from said field implant region, said source region being of a semiconductor material of said first conductivity type; a body contact region extending into said second semiconductor later from said upper surface of said second semiconductor layer, said body contact region contacting said source region, said source region being disposed between said body contact region and said field implant region, said body contact region being of a semiconductor materual of a second conductovoty type opposite said first conductivity type; a body region extending from said body contact region and underneath said source region, said body region extending between said source region and said field implant region to form a channel region at said upper surface of the second semiconductor layer between said source region and said field implant region, said body regin being separated from said field implant region by a drift region portion of said second semiconductor layer between said source region and said field implant region, said body contact region being of a semiconductor material of said second semiconductor type; and a polysilicon gate layer, said polysilicon gate layer extending from a location over said source region, over said channel region, and over said drift region portion of said second semiconductor layer.

公开(公告)号：EP0567341B1

公开(公告)日：1996-11-13

申请号：EP93303169.2

申请日：1993-04-22

申请人： SILICONIX INCORPORATED

发明人： Yilmaz, Hamza

IPC分类号： H01L29/772 ,  H01L29/72

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/7811

摘要： The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

公开(公告)号：EP0708482A2

公开(公告)日：1996-04-24

申请号：EP95116353.4

申请日：1995-10-17

申请人： SILICONIX Incorporated

发明人： Williams, Richard K. ,  Yilmaz, Hamza ,  Cornell, Michael E. ,  Chen, Jun Wei

IPC分类号： H01L21/8249 ,  H01L27/06

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7835 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.