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公开(公告)号：EP0588142A1
公开(公告)日：1994-03-23
申请号：EP93113859.8
申请日：1993-08-30
申请人： YOZAN INC. , SHARP KABUSHIKI KAISHA
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： The present invention has an object to provide a signal integration circuit for integrating weighted signal by a simple circuit.
The signal integration circuit disclosed here comprising the first MOSFET (T₁) including a drain connected to a power source (V cc ) and a gate connected to a plural number of the first capacitances (C₁-C n ) in parallel; and an input means (WS₁-WS n ) connected to each capacitance; in which each input means comprises; the second MOSFET (T₂) whose source is connected to the first capacitance through a resistance (R₁), which receives an input pulse signal (D₁), and whose gate is grounded through the second capacitance (Cg₃), and the third MOSFET (T₃) whose source is connected to a gate of the second MOSFET (T₂), whose drain is connected to a power source (V cc ), and whose gate receives a pulse signal for setting weight (W i ); a gate of the first MOSFET receiving a reference saw-tooth signal (RP), a source of the first MOSFET grounded through the third capacitance (Cg₁), and an output pulse signal being output from this source of said first MOSFET (T₁).摘要翻译： 本发明的目的是提供一种用于通过简单电路对加权信号进行积分的信号积分电路。 这里公开的信号积分电路包括第一MOSFET（T1），其包括连接到电源（Vcc）的漏极和并联连接到多个第一电容（C1-Cn）的栅极; 和连接到每个电容的输入装置（WS1-WSn）; 其中每个输入装置包括： 第二MOSFET（T2），其源极通过电阻（R1）与第一电容连接，电阻（R1）接收输入脉冲信号（D1），其栅极通过第二电容（Cg3）接地，第三MOSFET（T3 ），其源极连接到第二MOSFET（T2）的栅极，其漏极连接到电源（Vcc），并且其栅极接收用于设定重量（Wi）的脉冲信号; 接收参考锯齿信号（RP）的第一MOSFET的栅极，通过第三电容（Cg1）接地的第一MOSFET的源极和从该第一MOSFET（T1）的源极输出的输出脉冲信号。
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公开(公告)号：EP0874470A3
公开(公告)日：2003-04-16
申请号：EP98106808.3
申请日：1998-04-15
申请人： Yozan, Inc.
发明人： Zhou, Changming , Zhou, Xuping , Shou, Guoliang
CPC分类号： H04B1/1615 , H04W52/029 , Y02D70/40
摘要： A waiting circuit incorporated within a portable terminal of a mobile communication system, for detecting a predetermined signal from a base station so as to start other circuits in a sleep mode than the waiting circuit. The predetermined signal is generated in the base station at a speed of a predetermined symbol rate and modulated to be a intermediate frequency signal. The waiting circuit samples the intermediate frequency signal in response to a sampling clock of a speed of an integer times as quick as the symbol rate. The sampled signal is input to a matched filter for multiplying the sampled signal by a predetermined sequence of coefficients. This coefficients corresponds to the intermediate frequency signal sampled by the sub-sampling circuit.
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公开(公告)号：EP0763897A3
公开(公告)日：2002-09-04
申请号：EP96114838.4
申请日：1996-09-16
摘要： The present invention has an object to provide an A/D converting circuit with improved accuracy in an output. In this invention, the initial electric charge is given to a capacitive coupling for outputting in a quantizing circuit so as to cancel the dispersion of thresholds of MOS inverter in the quantizing circuit, the supply voltage of the first and the second inverters is higher than the supply voltage of an inverter for quantizing, as well as the initial electric charge is given to a capacitance for input in order to limit the function of the quantizing circuit within the linear area of the first and the second inverters.
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公开(公告)号：EP0756378B1
公开(公告)日：2001-10-24
申请号：EP96112146.4
申请日：1996-07-26
申请人： YOZAN INC. , SHARP KABUSHIKI KAISHA
CPC分类号： H03H11/04 , H03H17/0254
摘要： The present invention has an object to provide a matched filter with further reduced electric power. In a matched filter circuit according to the present invention, the electric power supply is stopped with respect to an unnecessary circuit according to an experience that signal is partially sampled just after the acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups"1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.
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公开(公告)号：EP0784385B1
公开(公告)日：1999-06-09
申请号：EP97100428.8
申请日：1997-01-13
发明人： Zhou, Changming , Shou, Guoliang , Urabe, Kenzo, c/o Kokusai Electric Co., Ltd , Miyatani, Tetsuhiko, c/o Kokusai Electric Co., Ltd
CPC分类号： H04B1/71075
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公开(公告)号：EP0874470A2
公开(公告)日：1998-10-28
申请号：EP98106808.3
申请日：1998-04-15
申请人： Yozan Inc.
发明人： Zhou, Changming , Zhou, Xuping , Shou, Guoliang
CPC分类号： H04B1/1615 , H04W52/029 , Y02D70/40
摘要： A waiting circuit incorporated within a portable terminal of a mobile communication system, for detecting a predetermined signal from a base station so as to start other circuits in a sleep mode than the waiting circuit. The predetermined signal is generated in the base station at a speed of a predetermined symbol rate and modulated to be a intermediate frequency signal.
The waiting circuit samples the intermediate frequency signal in response to a sampling clock of a speed of an integer times as quick as the symbol rate. The sampled signal is input to a matched filter for multiplying the sampled signal by a predetermined sequence of coefficients. This coefficients corresponds to the intermediate frequency signal sampled by the sub-sampling circuit.摘要翻译： 一种结合在移动通信系统的便携式终端内的等待电路，用于检测来自基站的预定信号，以便开始休眠模式中的其它电路等于等待电路。 在基站中以预定符号速率的速度生成预定信号，并将其调制为中频信号。 等待电路响应于与符号速率相同的整数倍的速度的采样时钟对中频信号进行采样。 采样信号被输入到匹配滤波器，用于将采样信号乘以预定的系数序列。 该系数对应于由次采样电路采样的中频信号。
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公开(公告)号：EP0871298A2
公开(公告)日：1998-10-14
申请号：EP98105989.2
申请日：1998-04-01
申请人： YOZAN INC.
发明人： Zhou, Changming , Shou, Guoliang
IPC分类号： H04B1/707
CPC分类号： H04B1/7093
摘要： The present invention provides a complex despreading system easily-arranged and small circuit by not setting pairs of adders at the output area. Using a complex matched filter for despreading received signals with a QPSK system in the primary modulation and BPSK in the secondary modulation, each I- and Q-channel multiplication and addition circuit input area includes a pair of adders. In one of these adders, the I-channel multiplication and addition circuit multiplies and adds a spread code to those added in-phase and quadrature components of a received signal. In the other adder of the pair, the circuit multiplies and adds a spread code to that in-phase component subtracted from the quadrature one.
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29.发明公开Demodulator for CDMA spread spectrum communication using multiple PN codes 失效DemodulatorfürCDMASpreizspektrumnachrichtenübertragungunter Verwendung einer Mehrzahl von PN-Koden
公开(公告)号：EP0790712A2
公开(公告)日：1997-08-20
申请号：EP97102710.7
申请日：1997-02-19
发明人： Zhou, Changming , Shou, Guoliang , Zhou, Xuping , Yamamoto, Makoto , Urabe, Kenzo , Takatori, Suano
IPC分类号： H04B1/707
CPC分类号： H04B1/7093
摘要： The demodulator has a plurality of matched filters in parallel. Each matched filter has a different binary PN code, a plurality of sample holders, a plurality of multipliers, an adder, and a controller. The sample holders has a common input, a switch, a first capacitor, a first inverse amplifier with an output and an input connected to the common input through the switch and the capacitor, and a first feedback capacitor for feeding the output of the first inverse amplifier back to the input. Each multiplier has a first and second sub-multiplexers, one of sub-multiplexer selecting corresponding sample holder output and another sub-multiplexer selecting a reference voltage.
摘要翻译： 解调器具有并联的多个匹配滤波器。 每个匹配滤波器具有不同的二进制PN码，多个采样保持器，多个乘法器，加法器和控制器。 样本保持器具有公共输入，开关，第一电容器，具有输出的第一反相放大器和通过开关和电容器连接到公共输入的输入端，以及用于馈送第一反相器的输出的第一反馈电容器 放大器返回输入。 每个乘法器具有第一和第二子复用器，子复用器中的一个选择对应的采样保持器输出，另一个副多路复用器选择参考电压。
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公开(公告)号：EP0709892A2
公开(公告)日：1996-05-01
申请号：EP95115447.5
申请日：1995-09-29
申请人： YOZAN INC. , SHARP KABUSHIKI KAISHA
IPC分类号： H01L27/105 , H01L23/522
CPC分类号： H01L27/0705 , H01L27/0203 , H01L27/0207 , H01L27/092 , H01L2924/0002 , H03K19/00384 , H01L2924/00
摘要： MOS inverter forming method within a large scale integrated circuit (LSI) for providing a pair of circuits with the same performance each of which comprise a plurality of MOS inverters serially connected from the first stage to the last stage, each the MOS inverters being provided with an input, characterized in that, the input of the MOS inverters of the first stage are adjacently positioned with facing to each other.
摘要翻译： 在大规模集成电路（LSI）中的MOS反相器形成方法，用于提供具有相同性能的一对电路，每个电路包括从第一级至最后级串联连接的多个MOS反相器，每个MOS反相器设置有 输入，其特征在于，所述第一级的MOS反相器的输入相邻地相邻地定位。
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