公开(公告)号：EP0817199A2

公开(公告)日：1998-01-07

申请号：EP97110765.1

申请日：1997-07-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： van der Wagt, Jan P.

IPC分类号： G11C11/36

CPC分类号： B82Y10/00 ,  G11C11/36 ,  G11C2211/5614

摘要： A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistance devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line. The memory cell comprises an FET having its gate coupled to a word line and one of its drain and source electrodes coupled to a bit line, first and second negative resistance devices 44,46 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the other of the drain and source electrodes, and a capacitance 48 coupled between the common point of the series-connected negative resistance devices.

公开(公告)号：EP0225698B1

公开(公告)日：1990-08-01

申请号：EP86307871.3

申请日：1986-10-10

申请人： FUJITSU LIMITED

发明人： Yokoyama, Naoki ,  Mori, Toshihiko

IPC分类号： G11C11/34 ,  G11C11/56 ,  H03K3/36 ,  H03K23/00 ,  H03K29/00

CPC分类号： B82Y10/00 ,  G11C11/34 ,  G11C11/36 ,  G11C11/39 ,  G11C11/56 ,  G11C2211/5614 ,  H03K3/36 ,  H03K23/00

公开(公告)号：EP0076139A2

公开(公告)日：1983-04-06

申请号：EP82305098.4

申请日：1982-09-28

申请人： UNISYS CORPORATION

发明人： Elmasry, Mohamed Ibrahim ,  Peterson, Luverne Ray

IPC分类号： G11C11/34 ,  G11C11/36

CPC分类号： G11C11/39 ,  G11C11/36

摘要： Disclosed is an improved static memory cell comprised of first and second conductive means for carrying respective bias voltages in the cell, a third conductive means for carrying an inpuvoutput voltage signal in the cell, and a Lambda diode coupled between the first and third conductive means for there providing a negative dynamic resistance whenever the input/output voltage signal is within a predetermined range between the bias voltages on the first and second conductive means, with the improvement being a voltage dependent resistance means coupled between the second and third conductive means for there providing a negative dynamic resistance in response to at least some of the input/output voltages within said range.